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参数资料
| 型号： | IDT88P8342BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 57/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8342BHGI |
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60
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
the DAT_PAR_ERR bit field. The LP affected by these two parity error bit fields
isenumeratedinthePORT_ADDRESSfield.ThebitfieldsofSPI-3egresstest
register are described. The bit fields are automatically cleared following the
generation of the associated error.
ADD_PAR_ERR
A single address parity error is introduced on a SPI-
3 egress LP through the ADD_PAR_ERR bit field. The LP affected by the
ADD_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
0=No parity error introduced
1=Introduce a single address parity error on a SPI-3 egress LP
DAT_PAR_ERR
A single data parity error is introduced on a SPI-3
egress LP through the DAT_PAR_ERR bit field. The LP affected by the
DAT_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
0=No parity error introduced
1=Introduce a single data parity error on a SPI-3 egress LP
PORT_ADDRESS
The LP affected by both the ADD_PAR_ERR and
theDAT_PAR_ERRbitfieldsisenumeratedinthePORT_ADDRESSfield.The
value of the PORT_ADDRESS is set from 0x00 to 0xFF.
SPI-3 egress fill level register (Block_base 0x0700
+ Register_offset 0x03)
There is one register for SPI-3 egress fill level register per SPI-3 interface.
Each register has read-only access. The bit fields of the SPI-3 egress fill level
register are described.
FILL_CUR
Current SPI-3 egress buffer fill level. Since this is a real-time
register, the value read from it will change rapidly and is used for internal
diagnosticsonly.
I_FCLK_AV Current SPI-3 egress clock availability is checked here.
0=SPI-3 egress clock transitions were not detected on a
SPI-3 port
1=SPI-3egressclocktransitionsweredetectedonaSPI-
3 port
SPI-3 egress max fill level register (Block_base
0x0700 + Register_offset 0x04)
TABLE 58 - SPI-3 EGRESS FILL LEVEL REGISTER
(REGISTER_OFFSET=0x03)
Field
Bits
Length
Initial Value
FILL_CUR
3:0
4
0x0
Reserved
4
1
0x0
E_FCLK_AV
5
1
0b0
TABLE 59 - SPI-3 EGRESS MAX FILL LEVEL REGIS-
TER(REGISTER_OFFSET=0x04)
Field
Bits
Length
Initial Value
FILL_MAX
3:0
4
0x0
ThereisoneregisterforSPI-3egressmaxfillLevelperSPI-3interface.Each
register has read-only access, and is cleared after reading. 0xF is the highest
filling level, meaning all egress buffers had been full at some time since the last
read of the FILL_MAX field. The units of FILL_MAX are one-sixteenth of the
available egress buffering. Each unit is equal to 128 bytes. The bit field of the
SPI-3 egress max fill Level register is described.
FILL_MAX
Maximum SPI-3 egress buffer fill level since the last read
of the SPI-3 egress Max Fill Level Register
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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