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| 型号： | IDT88P8342BHGI |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 63/98页 |
| 文件大小： | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 标准包装： | 24 |
| 系列： | * |
| 其它名称： | 88P8342BHGI |
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66
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
9.3.11 Block base 0x1600 registers
The SPI-4 ingress registers are at Block_base 0x1600.
SPI-4 ingress packet length configuration
(Block_base 0x1600 + Register_offset 0x00-0x3F)
TABLE 79 - SPI-4 INGRESS PACKET LENGTH
CONFIGURATION (64 ENTRIES CONFIGURABLE)
Field
Bits
Length
Initial Value
MIN_LENGTH
7:0
8
0x40
Reserved
15:8
8
0x0
MAX_LENGTH
29:16
14
0x5EE
There are two sets of 64 registers for SPI-4 ingress packet length configu-
ration, one per SPI-3 interface. Each register has read and write access. The
minimum and maximum packet lengths per LID are provisioned using the SPI-
4 ingress packet length configuration register. The bit fields of a SPI-4 ingress
packet length configuration register are described.
MIN_LENGTH
SPI-4 ingress minimum packet length. The minimum
packet length is programmed from 0 to 255 bytes. The resolution is one byte.
MAX_LENGTH SPI-4 ingress maximum packet length. The maximum
packetlengthisprogrammedfrom0to16,383bytes.Theresolutionisonebyte.
9.3.12 Block base 0x1700 registers
SPI-3 egress port descriptor table (Block_base
0x1700 + Register_offset 0x00-0x3F)
There are 64 SPI-3 egress port descriptor tables per SPI-3 egress port. The
SPI-3egressportdescriptortablehasreadandwriteaccess.TheSPI-3egress
per LID packet fragment length and direction are provisioned using the SPI-3
egressportdescriptortables.ThebitfieldsofaSPI-3egressportdescriptortable
are described.
MAX_BURST
SPI-3 packet fragment length for a SPI-3 egress LP. One
morethanMAX_BURSTfieldmultipliedbysixteenisthepacketfragmentlength
fortheLP.Forexample, programmingthenumber3intotheMAX_BURSTfield
results in a packet fragment length of (3+1) x 16 = 64 bytes. The MAX_BURST
field is used to prioritize traffic.
DIRECTION
TheSPI-3egresstrafficisdirectedtoaSPI-3egressport.
The Path selection is defined for each of the 64 LIDs by the associated
DIRECTION field as shown in the following table.
TABLE 80 - SPI-3 EGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
Field
Bits
Length
Initial Value
MAX_BURST
3:0
4
0x0F
Reserved
7:4
4
0x0
DIRECTION
8:9
2
0b11
Reserved
31:10
22
0x00
9.3.13 Block base 0x1800 registers
SPI-4 ingress port descriptor table (Block_base
0x1800 + Register_offset 0x00-0x3F)
There is one set of 64 registers for SPI-4 ingress port descriptors per SPI-
3 interface. The SPI-4 ingress port descriptor tables are 32 bits wide and have
read and write access. Each of the SPI-4 ingress port descriptor tables is used
tocontroltheamountofbufferingandthebackpressurethresholdoftheavailable
buffer segment pool for the SPI-4 ingress.
EachSPI-4ingressbuffersegmentpoolis128Kbytes,dividedinto508buffer
segments of 256 bytes per segment. The 508 buffer segments can be shared
amongtheLIDsinitiallyprogrammedbythenumericalfieldNR_LID.Oftheshare
of the buffer memory, a SPI-4 LID can be allocated the maximum number of
segments permitted, or can be programmed to fewer segments by decreasing
the M field. Decreasing M increases the chance of backpressure and possibly
buffer overflow, but can result in lower latency.
The FREE_SEGMENT_S (starving threshold) and FREE_SEGMENT_H
(hungry threshold) fields are used, along with the M field, to set the two
backpressuresettingsperLIDontheSPI-4ingress.TheFREE_SEGMENT_S
field must always be greater than the FREE_SEGMENT_H field.
M
Thenumberof256-bytebufferpoolsegmentsallocatedtoaLID.The
range of M is 0x000 to 0x1FC (508 base 10), but can not exceed the number
dictated by NR_LID [Block_base 0x1900 + Register_offset 0x00].
FREE_SEGMENT_S
This field is used to define the SPI-4 ingress per-LID starving backpressure
threshold based on the number of free buffer pool segments (M) available, as
follows:
THRESHOLD_S = N * FREE_SEGEMENT_S, where the value of N is
defined as:
DIRECTION
Path
00
SPI-3 physical
01
Reserved
10
Capture
11
Discard
TABLE 81 - SPI-3 EGRESS DIRECTION CODE
ASSIGNMENT
TABLE 82 - SPI-4 INGRESS PORT DESCRIPTOR
TABLES (64 ENTRIES)
Field
Bits
Length
Initial Value
M
8:0
9
0x000
Reserved
15:9
7
0x00
FREE_SEGMENT_S
20:16
5
0x00
Reserved
23:21
3
0x0
FREE_SEGMENT_H
28:24
5
0x00
Reserved
31:29
3
0x0
M[8:0]
N
0x1FF to 0x100
16
0x0FF to 0x080
8
0x07F to 0x040
4
0x03F to 0x020
2
0x01F to 0x000
1
FREE_SEGMENT_H
This field is used to define the SPI-4 ingress per-LID hungry backpressure
threshold based on the number of free buffer pool segments (M) available, as
follows:
THRESHOLD_H = N * FREE_SEGEMENT_H, where the value of N is as
defined for FREE_SEGEMENT_S.
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相关代理商/技术参数 |
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| IDT88P8342BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| IDT88P8344BHGI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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