参数资料
型号: IDT88P8342BHGI
厂商: IDT, Integrated Device Technology Inc
文件页数: 9/98页
文件大小: 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
标准包装: 24
系列: *
其它名称: 88P8342BHGI
17
IDT88P8342 SPI EXCHANGE 2 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
3.2 SPI-4
Refer to OIF SPI-4 document (see Glossary) for full details of the implemen-
tationagreement.
- Clock rate is 80 - 400 MHz (160 - 800MHz DDR)
- Link and PHY modes supported
- Address range 0 to 255 with support for 128 simultaneously active logical
ports
- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples
- 256 entry calendar
- LVTTL and LVDS status signals supported
The following are implemented for the SPI-4 interface:
- Link / PHY layer device
- Physical port active
3.2.1 SPI-4 ingress
The SPI-4 ingress includes
Bit alignment
Wordalignment/de-skew
Transfer decode and dispatch
PFPinterface
Statusframegeneration
SPI-4 ingress configurable parameters
SPI-4 LID map
- 256 entries, one per SPI-4 LP
- SPI-3 physical interface identifier
- Physical port enable
Word / bit synchronization
- LVDS clock data alignment and LVDS data de-skew
Minimum packet length
- Packets shorter than the minimum length will be optionally counted in the
short packet counter.
- Range 0 – 255 in 1 byte increments
Maximum packet length
- Packets longer than the maximum length will be optionally counted in the
long packet counter.
- Range 0 – 16,383 in 1 byte increments
Free segment backpressure threshold
-NumberoffreebuffersegmentsallocatedtotriggerbackpressurefortheLP
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