参数资料
| 型号： | ISL6324IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 14/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324
MOSFET
UGATE(n)
V IN
L
I
L
n
DCR
V OUT
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R SET resistor
will program all the effective internal R ISEN resistors to the
same value.
DRIVER
LGATE(n)
INDUCTOR
V L (s)
C OUT
Channel-Current Balance
One important benefit of multiphase operation is the thermal
V C (s)
advantage gained by distributing the dissipated heat over
ISL6323 INTERNAL CIRCUIT
R 1
C
R 2
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
I n
SAMPLE
V COMP
+
-
MODULATOR
RAMP
WAVEFORM
+
-
PWM1
TO GATE
CONTROL
LOGIC
FILTER
f(s)
+
-
V C (s)
R ISEN
ISENn-
ISENn+
I ER
-
I AVG
÷ N
Σ
I 4
I 3
I SEN
VCC
+
I 2
TO ACTIVE
CORE CHANNELS
{
RSET
I 1
TO NORTH BRIDGE
R SET
NOTE: Channel 3 and 4 are optional.
.
C SET
FIGURE 5. INDUCTOR DCR CURRENT SENSING
CONFIGURATION
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
In order to realize the thermal advantage, it is important that
L R 1 ? R
R 1 + R 2
------------- = -------------------- 2 - ? C
DCR
(EQ. 8)
each channel in a multiphase converter be controlled to
carry about the same amount of current at any load level. To
The capacitor voltage V C , is then replicated across the
effective internal sense resistor, R ISEN . This develops a
current through R ISEN which is proportional to the inductor
current. This current, I SEN , is continuously sensed and is
then used by the controller for load-line regulation,
channel-current balancing, and overcurrent detection and
limiting. Equation 9 shows that the proportion between the
channel current, I L , and the sensed current, I SEN , is driven
by the value of the effective sense resistance, R ISEN , and
the DCR of the inductor.
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I n ,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I AVG , provides a measure of the total load
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
I SEN = I L ? ------------------
DCR
R ISEN
(EQ. 9)
balance method is illustrated in Figure 6, with error
correction for Channel 1 represented. In the figure, the cycle
average current, I AVG , is compared with the Channel 1
The effective internal R ISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R ISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, R SET , from the RSET pin to the
VCC pin programs the effective internal R ISEN resistance
according to Equation 10.
sample, I 1 , to create an error signal I ER .
The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
I ER toward zero. The same method for error signal
correction is applied to each active channel.
VID Interface
The ISL6324 supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
R ISEN = ---------- ? R SET
3
400
14
(EQ. 10)
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
pin is used to command the ISL6324 into either the PVI
mode or the SVI mode. Whenever the EN pin is held LOW,
FN6518.2
September 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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