参数资料
型号: ISL6324IRZ-T
厂商: Intersil
文件页数: 16/38页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48-QFN
标准包装: 4,000
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL6324
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
METAL_VID
V_SVI
METAL_VID
V_SVI
VDD AND VDDNB
VDDPWRGD
VFIXEN
FIGURE 7. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID START-UP
PRE-PWROK METAL VID
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the
POR circuitry is satisfied, the ISL6324 begins decoding the
inputs per Table 2. Once the EN input exceeds the rising
enable threshold, the ISL6324 saves the Pre-PWROK metal
VID value in an on-board holding register and passes this
target to the internal DAC circuitry.
TABLE 2. PRE-PWROK METAL VID CODES
The VDD and VDDNB planes will linearly decrease to near
zero.
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
ISL6324 is designed to support the potential change of state
of these inputs. If VFIXEN is high, the IC decodes the SVC
and SVD states per Table 3.
Once enabled, the ISL6324 begins to soft-start both VDD
SVC
0
0
1
1
SVD
0
1
0
1
OUTPUT VOLTAGE (V)
1.1
1.0
0.9
0.8
and VDDNB planes to the programmed VFIX level. The
internal soft-start circuitry slowly stair steps the reference up
to the target value and this results in a controlled ramp of the
power planes. Once soft-start has ended and both output
planes are within regulation limits, the VDDPWRGD pin
transitions high. If the EN input falls below the enable falling
threshold, then the controller ramps both VDD and VDDNB
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
down to near zero.
TABLE 3. VFIXEN VID CODES
ISL6324 passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded
Pre-PWROK metal VID output level. The digital soft-start
circuitry actually stair steps the internal reference to the
target gradually over a fix interval. The controlled ramp of
both output voltage planes reduces in-rush current during
SVC
0
0
1
1
SVD
0
1
0
1
OUTPUT VOLTAGE (V)
1.4
1.2
1.0
0.8
the soft-start interval. At the end of the soft-start interval, the
VDDPWRGD output transitions high indicating both output
planes are within regulation limits.
If the EN input falls below the enable falling threshold, the
ISL6324 ramps the internal reference voltage down to near
zero. The VDDPWRGD de-asserts with the loss of enable.
16
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6324 to prepare for SVI
commands. The controller actively monitors the SVI
interface for set VID commands to move the plane voltages
FN6518.2
September 25, 2008
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