参数资料
| 型号： | ISL6324IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324
Voltage Regulation
The integrating compensation network shown in Figure 8
insures that the steady-state error in the output voltage is
limited only to the error in the reference voltage,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6324 to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is used by the
modulator to generate the PWM signals. The PWM signals
control the timing of the Internal MOSFET drivers and
regulate the converter output so that the voltage at FB is equal
to the voltage at REF. This will regulate the output voltage to
be equal to Equation 11. The internal and external circuitry
that controls voltage regulation is illustrated in Figure 8.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I AVG , flows from FB
through a load-line regulation resistor R FB . The resulting
voltage drop across R FB is proportional to the output current,
effectively creating an output voltage droop with a
steady-state value defined as in Equation 12:
V OUT = V REF – V DROOP
(EQ. 11)
V DROOP = I AVG ? R FB
(EQ. 12)
V OUT = V REF – ? ------------- ? DCR ? ? ---------- ? --------------- ? ? K ? R FB ?
R SET ?
? 3
The ISL6324 incorporates differential remote-sense
amplification in the feedback path. The differential sensing
removes the voltage error encountered when measuring the
output voltage relative to the controller ground reference point
resulting in a more accurate means of sensing output voltage.
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
shown in Equation 13.
? I OUT 400 1 ?
? N ?
EXTERNAL CIRCUIT
FS
ISL6324 INTERNAL CIRCUIT
(EQ. 13)
In Equation 13, V REF is the reference voltage, I OUT is the
R FS
COMP
DROOP
CONTROL
TO
OSCILLATOR
total output current of the converter, K is the DC gain of the
RC filter across the inductor (K is defined in Equation 7), N is
the number of active channels, and DCR is the Inductor
DCR value.
C C
R C
I AVG
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
R FB
+
V DROOP
-
FB
-
+
V COMP
ERROR
AMPLIFIER
passes only the target voltage to the ISL6324 through either
the PVI or SVI interface. The ISL6324 manages the resulting
VID-on-the-Fly transition in a controlled manner, supervising
a safe output voltage transition without discontinuity or
disruption. The ISL6324 begins slewing the DAC at
3.25mV/μs until the DAC and target voltage are equal. Thus,
the total time required for a dynamic VID transition is
+
V OUT
VSEN
∑
+
+
VID
DAC
dependent only on the size of the DAC change.
To further improve dynamic VID performance, ISL6324 also
implements a proprietary DAC smoothing feature. The
-
RGND
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
VID-on-the-fly transition.
REGULATION
Compensating Dynamic VID Transitions
Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution that can help to
reduce the output-voltage spike that results from fast
load-current demand changes.
18
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R FB , and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
FN6518.2
September 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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