参数资料
型号: ISL6324IRZ-T
厂商: Intersil
文件页数: 27/38页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48-QFN
标准包装: 4,000
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL6324
? ? ------ + I ----------- ? ? t
? I ?
? I
+ ? ------ – ----------- ? ? t
2 ? ?
? N
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
.
P
LOW , 2
= V
D ( ON )
? f
S
M P-P
? N 2 ?
d1
?
?
M I P-P
d2
I M
I P-P
P UP ( 1 ) ≈ V IN ? ? ------ + ---------- ? ? ? ---- 1 ? ? f S
? t ?
? N
2 ? ? 2 ?
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following sections. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials and example board layouts for all common
microprocessor applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination depends
heavily on the cost analysis which in turn depends on system
constraints that differ from one design to the next. Principally,
the designer will be concerned with whether components can
be mounted on both sides of the circuit board, whether
through-hole components are permitted, the total board space
available for power supply circuitry, and the maximum amount
of load current. Generally speaking, the most economical
solutions are those in which each phase handles between
25A and 30A. All surface-mount designs will tend toward the
lower end of this current range. If through-hole MOSFETs and
inductors can be used, higher per-phase currents are
possible. In cases where board space is the limiting
constraint, current can be pushed as high as 40A per phase,
but these designs require heat sinks and forced air to cool the
MOSFETs, inductors and heat dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
(EQ. 20)
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P LOW,1 and P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to r DS(ON) losses, a large portion of the upper
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent on
switching frequency, the power calculation is more complex.
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse recovery charge, Q rr ,
and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 21,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP(1) .
(EQ. 21)
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 22, the
approximate power loss is P UP(2) .
P UP ( 2 ) ≈ V IN ? ? ------ – ---------- ?
? ? ---- 2 ? ? f S
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
? I M I P-P ?
? N 2 ?
? t ?
? 2 ?
(EQ. 22)
I L ( P – P ) ? ( 1 – d )
? I M ? 2
P LOW , 1 = r DS ( ON ) ? ? ------ ? ? ( 1 – d ) + ---------------------------------------------- (EQ. 19)
P UP ( 3 ) = V IN ? Q rr ? f S
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r DS(ON) ). In Equation 19, I M is the maximum continuous
output current, I P-P is the peak-to-peak inductor current (see
Equation 2), and d is the duty cycle (V OUT /V IN ).
2
? N ? 12
A third component involves the lower MOSFET
reverse-recovery charge, Q rr . Since the inductor current has
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP(3) as shown in
Equation 23.
(EQ. 23)
Finally, the resistive part of the upper MOSFET is given in
I P-P 2
? I M ?
P UP ( 4 ) ≈ r DS ( ON ) ? ? ------ ? ? d + ----------
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
Equation 24 as P UP(4) .
2
? N ? 12
(EQ. 24)
diode forward voltage at I M , V D(ON) , the switching
frequency, f S , and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
27
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 21, 22, 23 and 24. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
FN6518.2
September 25, 2008
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