参数资料
型号: ISL6324IRZ-T
厂商: Intersil
文件页数: 28/38页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48-QFN
标准包装: 4,000
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL6324
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
Schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 25:
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See “Layout Considerations” on
page 35 for thermal transfer improvement suggestions.
When designing the ISL6324 into an application, it is
recommended that the following calculations is used to
ensure safe operation at the desired frequency for the
C BOOT_CAP ≥ --------------------------------------
Q GATE
Δ V BOOT_CAP
(EQ. 25)
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
Q GATE = ------------------------------------ ? N Q1
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
P Qg_Q1 = --- ? Q G1 ? PVCC ? f SW ? N Q1 ? N PHASE
Q G1 ? PVCC
V GS1
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
average driver current can be estimated with Equations 26
and 27, respectively.
(EQ. 26)
3
2
P Qg_Q2 = Q G2 ? PVCC ? f SW ? N Q2 ? N PHASE
I DR = ? --- ? Q G1 ? N
1.6
1.4
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? f SW + I Q (EQ. 27)
1.2
1.0
0.8
0.6
Q GATE = 100nC
In Equations 26 and 27, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1 and
N Q2 are the number of upper and lower MOSFETs per phase,
0.4
0.2
20nC
50nC
respectively; N PHASE is the number of active phases. The
I Q *VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PVCC
BOOT
Δ V BOOT_CAP (V)
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
C GD
D
Gate Drive Voltage Versatility
R HI1
UGATE
G
C DS
The ISL6324 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
R LO1
R G1
R GI1
C GS
Q1
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
PHASE
S
rail voltages simultaneously.
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
28
FN6518.2
September 25, 2008
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