参数资料
型号: ISL6324IRZ-T
厂商: Intersil
文件页数: 15/38页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48-QFN
标准包装: 4,000
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL6324
both the multiphase Core and single-phase North Bridge
TABLE 1. 6-BIT PARALLEL VID CODES (Continued)
Regulators are disabled and the ISL6324 is continuously
sampling voltage on the VID1/SEL pin. When the EN pin is
toggled HIGH, the status of the VID1/SEL pin will latch the
ISL6324 into either PVI or SVI mode. This latching occurs on
the rising edge of the EN signal.If the VID1/SEL pin is held
LOW during the latch, the ISL6324 will be placed into SVI
mode. If the VID1/SEL pin is held HIGH during the latch, the
ISL6324 will be placed into PVI mode. For the ISL6324 to
properly enter into either mode, the level on the VID1/SEL
pin must be stable no less that 1μs prior to the EN signal
transitioning from low to high.
6-bit Parallel VID Interface (PVI)
With the ISL6324 in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multiphase controller is
active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
TABLE 1. 6-BIT PARALLEL VID CODES
VID5
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID4
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VREF
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VREF
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
0
1
0
1
0
0
1.0500
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
Serial VID Interface (SVI)
The on-board Serial VID interface (SVI) circuitry allows the
processor to directly drive the core voltage and Northbridge
voltage reference level within the ISL6324. The SVC and SVD
states are decoded with direction from the PWROK and
VFIXEN inputs as described in the following sections. The
ISL6324 uses a digital to analog converter (DAC) to generate a
reference voltage based on the decoded SVI value. See
Figure 7 for a simple SVI interface timing diagram.
15
FN6518.2
September 25, 2008
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