参数资料
| 型号： | ISL6324IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 24/38页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
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ISL6324
.
SDA
SCL
ISL6324 I 2 C Slave Address
All devices on the I 2 C bus must have a 7-bit I 2 C address in
order to be recognized. The address for the ISL6324 is
1000_110.
Communicating Over the I 2 C Bus
DATA LINE
STABLE
CHANGE
OF DATA
Two transactions are supported on the I 2 Cbus:
DATA VALID ALLOWED
FIGURE 15. DATA VALIDITY
START and STOP Conditions
Figure 16 shows a START (S) condition is a HIGH to LOW
transition of the SDA line while SCL is HIGH.
The STOP (P) condition is a LOW to HIGH transition on the
SDA line while SCL is HIGH. A STOP condition must be sent
before each START condition (see Figure 16).
SDA
SCL
1. Write register
2. Read register from current address.
All transactions start with a control byte sent from the I 2 C
master device. The control byte begins with a Start condition,
followed by 7 bits of slave address. The last bit sent by the
master is the R/W bit and is 0 for a write or 1 for a read. If
any slaves on the I 2 C bus recognize their address, they will
Acknowledge by pulling the serial data line low for the last
clock cycle in the control byte. If no slaves exist at that
address or are not ready to communicate, the data line will
be 1, indicating a Not Acknowledge condition.
Once the control byte is sent, and the ISL6324 acknowledges
it, the 2nd byte sent by the master must be a register address
byte. This register address byte tells the ISL6324 which one of
S
P
the two internal registers it wants to write to or read from. The
START STOP
CONDITION CONDITION
FIGURE 16. START AND STOP WAVEFORMS
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB) and the least significant bit last (LSB).
Acknowledge
Each address and data transmission uses 9-clock pulses.
The ninth pulse is the acknowledge bit (A). After the start
condition, the master sends 7 slave address bits and a R/W
bit during the next 8-clock pulses. During the ninth clock
pulse, the device that recognizes its own address holds the
data line low to acknowledge. The acknowledge bit is also
used by both the master and the slave to acknowledge
receipt of register addresses and data as described in
Figure 17.
address of the first internal register, RGS1, is 0000_0000.
This register sets the North Bridge Offset, Overvoltage trip
point and Power Good trip level. The address of the second
internal register, RGS2, is 0000_0001. This register sets the
Core Offset, Overvoltage trip point and Power Good trip level.
Once the ISL6324 receives a correct register address byte, it
responds with an acknowledge.
Writing to the Internal Registers
In order to change any of the three operating parameters via
the I 2 C bus, the internal registers must be written to. The two
registers inside the ISL6324 can be written individually with
two separate write transactions or sequentially with one write
transaction by sending two data bytes. See “Reading from
the Internal Registers” on page 25.
To write to a single register in the ISL6324, the master sends
a control byte with the R/W bit set to 0, indicating a write. If it
receives an Acknowledge from the ISL6324, it sends a
register address byte representing the internal register it
wants to write to (0000_0000 for RGS1 or 0000_0001 for
SCL
1
2
8
9
RGS2). The ISL6324 will respond with an Acknowledge. The
master then sends a byte representing the data byte to be
written into the desired register. The ISL6324 will respond
SDA
MSB
with an Acknowledge. The master then issues a Stop
condition, indicating to the ISL6324 that the current
transaction is complete. Once this transaction completes,
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 17. ACKNOWLEDGE ON THE I 2 C BUS
24
the ISL6324 will immediately update and change the
operating parameters on-the-fly.
It is also possible to write to both registers sequentially. To
do this the master must write to register RGS1 first. This
transaction begins with the master sending a control byte
with the R/W bit set to 0. If it receives an Acknowledge from
FN6518.2
September 25, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326AIRZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6326BCRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BCRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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