参数资料
型号: ISL6324IRZ-T
厂商: Intersil
文件页数: 22/38页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48-QFN
标准包装: 4,000
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 带卷 (TR)
ISL6324
I OCP = 100 μ A ? ------------- ? ---- ? ? ---------- ? R SET ? – ? ---------------------------------------- ? ---------------- ?
2 ? L ? f S
DCR K ? 400 ?
Overvoltage Protection
The ISL6324 constantly monitors the sensed output voltage
on the VSEN pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level and
exceeds the VDDPWRGD OV limit actions are taken by the
ISL6324 to protect the microprocessor load.
At the inception of an overvoltage event, both on-board
lower gate pins are commanded low as are the active PWM
outputs to the external drivers, the VDDPWRGD signal is
driven low, and the ISL6324 latches off normal PWM action.
This turns on the all of the lower MOSFETs and pulls the
output voltage below a level that might cause damage to the
load. The lower MOSFETs remain driven ON until VDIFF
falls below 400mV. The ISL6324 will continue to protect the
load in this fashion as long as the overvoltage condition
on page 13 and “Channel-Current Balance” on page 14 for
more detail on how the average current is measured. Once
the average current exceeds 100μA, a comparator triggers
the converter to begin overcurrent protection procedures.
The Core regulator and the North Bridge regulator have the
same type of overcurrent protection.
The overcurrent trip threshold is dictated by the DCR of the
inductors, the number of active channels, the DC gain of the
inductor RC filter and the R SET resistor. The overcurrent trip
threshold is shown in Equation 18.
N 1 3 ? V IN – N ? V OUT V OUT ?
? V IN ?
(EQ. 18)
Where:
R 2
recurs. Once an overvoltage condition ends the ISL6324
latches off, and must be reset by toggling POR, before a
soft-start can be re-initiated.
K = ---------------------
R 1 + R 2
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6324 is designed to protect either load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10k Ω resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
MOSFET should have a gate threshold well below the
maximum voltage rating of the load/microprocessor.
In the event that during normal operation the PVCC or VCC
voltage falls back below the POR threshold, the pre-POR
overvoltage protection circuitry reactivates to protect from
any more pre-POR overvoltage events.
Undervoltage Detection
The undervoltage threshold is set at VDAC - 300mV typical.
When the output voltage (VSEN-RGND) is below the
undervoltage threshold, VDDPWRGD gets pulled low. No
other action is taken by the controller. VDDPWRGD will
return high if the output voltage rises above VDAC - 250mV
typical.
Open Sense Line Protection
In the case that either of the remote sense lines, VSEN or
GND, become open, the ISL6324 is designed to detect this
and shut down the controller. This event is detected by
monitoring small currents that are fed out the VSEN and
RGND pins. In the event of an open sense line fault, the
controller will continue to remain off until the fault goes away,
at which point the controller will re-initiate a soft-start
sequence.
Overcurrent Protection
The ISL6324 takes advantage of the proportionality between
the load current and the average current, I AVG , to detect an
overcurrent condition. See “Continuous Current Sampling”
22
f S = Switching Frequency
Equation 18 is valid for both the Core regulator and the
North Bridge regulator. This equation includes the DC load
current as well as the total ripple current contributed by all
the phases. For the North Bridge regulator, N is 1.
During soft-start, the overcurrent trip point is boosted by a
factor of 1.4. Instead of comparing the average measured
current to 100μA, the average current is compared to 140μA.
Immediately after soft-start is over, the comparison level
changes to 100μA. This is done to allow for start-up into an
active load while still supplying output capacitor in-rush
current.
CORE REGULATOR OVERCURRENT
At the beginning of overcurrent shutdown, the controller sets
all of the UGATE and LGATE signals low, puts PWM3 and
PWM4 (if active) in a high-impedance state, and forces
VDDPWRGD low. This turns off all of the upper and lower
MOSFETs. The system remains in this state for fixed period of
12ms. If the controller is still enabled at the end of this wait
period, it will attempt a soft-start, as shown in Figure 14. If the
fault remains, the trip-retry cycles will continue until either the
fault is cleared or for a total of seven attempts. If the fault is
not cleared on the final attempt, the controller disables
UGATE and LGATE signals for both Core and North Bridge
and latches off requiring a POR of VCC to reset the ISL6324.
It is important to note that during soft-start, the overcurrent
trip point is increased by a factor of 1.4. If the fault draws
enough current to trip overcurrent during normal run mode, it
may not draw enough current during the soft-start ramp
period to trip overcurrent while the output is ramping up. If a
fault of this type is affecting the output, then the regulator will
complete soft-start and the trip-retry counter will be reset to
zero. Once the regulator has completed soft-start, the
overcurrent trip point will return to it’s nominal setting and an
FN6518.2
September 25, 2008
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