参数资料
型号: LFXP2-17E-7F484C
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: FPGA
中文描述: FPGA, 420 MHz, PBGA484
封装: 23 X 23 MM, FPBGA-484
文件页数: 50/92页
文件大小: 1701K
代理商: LFXP2-17E-7F484C
3-10
DC and Switching Characteristics
Lattice Semiconductor
LatticeXP2 Family Data Sheet
BLVDS
The LatticeXP2 devices support the BLVDS standard. This standard is emulated using complementary LVCMOS
outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when
multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one
possible solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Table 3-2. BLVDS DC Conditions
1
Over Recommended Operating Conditions
Parameter
Description
Typical
Units
Zo = 45
Zo = 45
VCCIO
Output Driver Supply (+/- 5%)
2.50
V
ZOUT
Driver Impedance
10.00
RS
Driver Series Resistor (+/- 1%)
90.00
RTL
Driver Parallel Resistor (+/- 1%)
45.00
90.00
RTR
Receiver Termination (+/- 1%)
45.00
90.00
VOH
Output High Voltage (After RTL)
1.38
1.48
V
VOL
Output Low Voltage (After RTL)
1.12
1.02
V
VOD
Output Differential Voltage (After RTL)
0.25
0.46
V
VCM
Output Common Mode Voltage
1.25
V
IDC
DC Output Current
11.24
10.20
mA
1. For input buffer, see LVDS table.
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
R
TL
R
TR
R
S = 90 ohms
R
S = 90 ohms
R
S =
90 ohms
R
S =
90 ohms
R
S =
90 ohms
R
S =
90 ohms
R
S =
90 ohms
R
S =
90 ohms
45-90
ohms
45-90
ohms
2.5V
+
-
. . .
+
-
. . .
+
-
+
-
16mA
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