![](http://datasheet.mmic.net.cn/30000/MC68EN360FE33_datasheet_2368935/MC68EN360FE33_250.png)
System Integration Module (SIM60)
6-6
MC68360 USER’S MANUAL
the bus. (The IDMA and SDMA have the ability to configure their bus arbitration level as
described in Section 7 Communication Processor Module (CPM)).
Figure 6-2. System Configuration and Protection Logic
6.3.1.1 SIM60 INTERRUPT GENERATION. An overview of the QUICC interrupt structure
is shown in
Figure 6-3. The lower half of the figure shows the SIM60. The SIM60 receives
interrupts from internal sources, such as the SWT and PIT, and external sources, such as
the IRQ7–IRQ1 lines.
If it generates an interrupt, the SWT always uses level 7; the PIT may use any level. The
IRQx pins choose the interrupt level associated with the pin (i.e., IRQ1 generates a level 1
interrupt, etc.). In addition, the CPM block may choose any level (1–7) for its interrupts.
The IMB architecture allows multiple interrupt sources to safely exist at the same level, a
process called interrupt arbitration. Once an interrupt acknowledge cycle occurs at the inter-
rupt level that matches a pending interrupt request, interrupt arbitration begins on the IMB.
The interrupt arbitration process is designed to choose between multiple requests at the
same level. For instance, if the PIT request is at level 4 but the CPM simultaneously is
requesting an interrupt at level 4, an interrupt arbitration process is required to decide who
wins the interrupt. (The interrupt arbitration process does not affect users who assign all
interrupt sources in the system to a unique interrupt level (1–7)).
SOFTWARE
WATCHDOG
PERIODIC
INTERRUPT TIMER
CLOCK
RESET
STATUS
2
PRESCALER
9
MODULE
CONFIGURATION
BUS
MONITOR
SPURIOUS
INTERRUPT MONITOR
DOUBLE BUS
FAULT MONITOR
SYSTEM RESET
INTERNAL BERR
IS SIGNALED
SYSTEM RESET
OR LEVEL 7
INTERRUPT
LEVEL 1 TO 7
INTERRUPT
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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