Serial Communication Controllers (SCCs)
MC68360 USER’S MANUAL
Figure 7-64. Sending Transparent Frames Between QUICCs
QUICC1 and QUICC2 exchange transparent frames and synchronize each other using the
RTS and CD pins. The CTS pin is not required since transmission may begin at any time.
Thus, the RTS signal is directly connected to the other QUICC’s CD pin. The RSYN option
in GSMR is not used, and transmission and reception from each QUICC are independent.
7.10.21.5 TRANSPARENT MEMORY MAP. When configured to operate in transparent
mode, the QUICC overlays the structure listed in Table 7-5 onto the protocol-specific area
of the SCC parameter RAM listed in Table 7-10.
NOTE: The boldfaced items should be initialized by the user.
Table 7-10. Transparent-Specific Parameters
Address
Name
Width
Description
SCC Base + 30
CRC_P
Long
CRC Preset for Totally Transparent
SCC Base + 34
CRC_C
Long
CRC Constant for Totally Transparent Receiver
TXD
RTS
FIRST BIT OF FRAME DATA
LAST BIT OF FRAME DATA OR CRC
BRGOx
(OUTPUT
IS CLKx
INPUT)
(OUTPUT
IS RXD
INPUT)
(OUTPUT
IS CD
INPUT)
NOTES:
1. CTS should be configured as always asserted in the port C parallel I/O or else connected to ground externally.
2. The required GSMR configurations are: DIAG = 00, CTSS = 1, CTSP is a don't care, CDS = 1, CDP = 0, TTX = 1, and
TRX = 1. REVD and TCRC are application dependent.
3. The transparent frame will contain a CRC if the TC bit is set in the Tx BD.
QUICC 1
QUICC 2
TXD
RTS
RXD
CD
RTS
TXD
RXD
BRGOx
CLKx
NOTES:
1. Each QUICC generates its own transmit clocks. If the transmit and receive clocks are the same, it is possible for one
QUICC to generate transmit and receive clocks for the other QUICC (for example, CLKx on QUICC 2 could be used to
clock the transmitter and receiver).
BRGOx
CLKx
CD LOST CONDITION
TERMINATES RECEPTION
OF FRAME
L = 1 IN TX BD CAUSES
NEGATION OF RTS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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