Serial Communication Controllers (SCCs)
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MC68360 USER’S MANUAL
Tx Data Buffer Pointer
The transmit buffer pointer, which always points to the first byte of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
7.10.20.14 BISYNC EVENT REGISTER (SCCE). The SCCE is called the BISYNC event
register when the SCC is operating as a BISYNC controller. It is a 16-bit register used to
report events recognized by the BISYNC channel and to generate interrupts. On recognition
of an event, the BISYNC controller will set the corresponding bit in the BISYNC event reg-
ister. Interrupts generated by this register may be masked in the BISYNC mask register.
The BISYNC event register is a memory-mapped register that may be read at any time. A
bit is reset by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be reset at a time. All unmasked bits must be reset before the CP will negate the inter-
nal interrupt request signal. This register is cleared at reset.
Bits 15–13, 9, 8, 6, 5—Reserved
GLr—Glitch on Rx
A clock glitch was detected by this SCC on the receive clock.
GLt—Glitch on Tx
A clock glitch was detected by this SCC on the transmit clock.
DCC—DPLL CS Changed
The carrier sense status as generated by the DPLL has changed state. The real-time sta-
tus may be found in SCCS. This is not the CD pin status that is discussed elsewhere; it is
only valid when the DPLL is used.
GRA—Graceful Stop Complete
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any mes-
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GLr
GLt
DCC
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GRA
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TXE
RCH
BSY
TX
RX
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