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Serial Communication Controllers (SCCs)
7-174
MC68360 USER’S MANUAL
occur; a zero represents a masked bit position. Upon an address match, the address and
the data following are written into the data buffers. When the addresses are not matched
and the frame is error-free, the nonmatching address received counter (NMARC) is incre-
mented.
NOTE
For 8-bit addresses, mask out (clear) the eight high-order bits in
the HMASK register.
The eight low-order bits of HMASK and HADDRx should contain
the address byte that immediately follows the opening flag. Ex-
ample: To recognize a frame that begins $7E (Flag), $68, $AA,
using 16-bit address recognition, HADDRx should contain
$AA68, and HMASK should contain $FFFF (see Figure 7-51).
Figure 7-51. HDLC Address Recognition Example
RFTHR. The received frames threshold value is used to reduce the interrupt overhead that
might otherwise occur when a series of short HDLC frames arrives, each causing an RXF
interrupt. By setting the RFTHR value, the user can limit the frequency of RXF interrupts.
The RXF interrupt will only occur when the RFTHR value is reached. RFCNT is a down-
counter used to implement this feature.
NOTE
The user should provide enough empty Rx BDs to receive the
number of frames specified in RFTHR.
7.10.17.5 HDLC PROGRAMMING MODEL. The CPU32+ core configures each SCC to
operate in one of the protocols by the MODE bits in the GSMR. The HDLC controller uses
the same data structure as in all other modes. This data structure supports multibuffer oper-
ation and address comparisons.
HMASK
8-BIT ADDRESS RECOGNITION
ADDRESS
$68
CONTROL
$44
FLAG
$7E
ADDRESS
$AA
ETC.
16-BIT ADDRESS RECOGNITION
$FFFF
$AA68
$FFFF
$AA68
RECOGNIZES ONE 16-BIT ADDRESS (HADDR1) AND
THE 16-BIT BROADCAST ADDRESS (HADDR2).
HMASK
ADDRESS
$55
CONTROL
$44
FLAG
$7E
ETC.
$00FF
$XX55
RECOGNIZES A SINGLE 8-BIT ADDRESS (HADDR1).
HADDR1
HADDR2
HADDR3
HADDR4
HADDR1
HADDR2
HADDR3
HADDR4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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