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Serial Management Controllers (SMCs)
MC68360 USER’S MANUAL
Fractional Stop Bits
Built-In Multidrop Modes
Freeze Mode for Implementing Flow Control
Isochronous Operation (1x Clock)
Interrupts upon Receiving Special Control Characters
Ability To Transmit Data on Demand using the TODR
SCCS Register To Determine Idle Status of the Receive Pin
Other Features for the SCCs as Described in the GSMR
The SMCs in UART mode, however, do provide one feature not provided by the regular
SCCs. The SMCs allow a data length option of up to 14 bits; whereas, the SCCs provide a
data length up to 8 bits. See Figure 7-75 for the SMC UART frame format.
Figure 7-75. SMC UART Frame Format
7.11.7.3 SMC UART MEMORY MAP. When configured to operate in UART mode, the
QUICC overlays the structure listed in Table 7-5 with the UART-specific parameters
described in Table 7-13.
MAX_IDL. Once a character of data is received on the line, the UART controller begins
counting any idle characters received. If a MAX_IDL number of idle characters is received
before the next data character is received, an idle timeout occurs, and the buffer is closed.
This, in turn, can produce an interrupt request to the CPU32+ core to receive the data from
Table 7-13. SMC UART-Specific Parameter RAM
Address
Name
Width
Description
SMC Base + 28
MAX_IDL
Word
Maximum Idle Characters
SMC Base + 2A
IDLC
Word
Temporary Idle Counter
SMC Base + 2C
BRKLN
Word
Last Received Break Length
SMC Base + 2E
BRKEC
Word
Receive Break Condition Counter
SMC Base +30
BRKCR
Word
Break Count Register (Transmit)
SMC Base +32
R_mask
Word
Temporary Bit Mask
SMTXD
SMCLK
16
×
START
BIT
5 TO 14 DATA BITS WITH THE
LEAST SIGNIFICANT BIT FIRST
PAR.
BIT
OPTIONAL
1 OR 2
STOP BITS
(CLOCK NOT TO SCALE)
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Freescale Semiconductor, Inc.
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