System Integration Module (SIM60)
6-48
MC68360 USER’S MANUAL
The address space bits for 040 type MPU are:
AS8—Not Relevant for 040 Cycles
AS7—Acknowledge Access(TT1-TT0=11)
AS6—Supervisor Code Access(TT1-TT0=00, TM2-TM0=110)
AS5—Supervisor Data Access(TT1-TT0=00, TM2-TM0=101)
AS4—MMU Table search Code Access (TT1-TT0=00, TM2-TM0=100)
AS3—MMU Table search Data Access(TT1-TT0=00, TM2-TM0=011)
AS2—User Code Access(TT1-TT0=00, TM2-TM0=010)
AS1—User Data Access(TT1-TT0=00, TM2-TM0=001)
AS0—Data Cache Push Access(TT1-TT0=00, TM2-TM0=000)
For each address space bit:
0 = A breakpoint match can occur for this address space.
1 = Mask this address space from the breakpoint match logic. No breakpoint match will
occur if this address space is used on a bus access.
V—Valid
This bit indicates when the contents of the breakpoint address register and breakpoint
control register pair are valid. BKPT signal will not be asserted unless the valid bit is set.
0 = Contents not valid.
1 = Contents valid.
6.9.4 Port E Pin Assignment Register (PEPAR)
The PEPAR controls the I/O pins associated with the EBI. Refer to Section 4 Bus Operation
for more information about the EBI. Port E pins can be independently programmed to be
either CAS3–CAS0 or IACK6 and IACK3–IACK1; AVEC (or AVECO) or IACK5; CS3 or
IACK7; AMUX or OE; A31–A28 or WE3–WE0.
Until the low byte of PEPAR is written, the WE3–WE0/A31–A28 pins are three-stated. The
PWW bit indicates whether the low byte of PEPAR was written. PEPAR may be read or writ-
ten at any time.
Bits 15, 11, and 3—Reserved
15
14
13
12
11
10
9
8
—
SINTOUT
—
CF1MODE
IPIPE1/
RAS1DD
00000000
76543210
A28–A31
WE0–WE3
OE/
AMUX
PWW
CAS2, 3
IACK3, 6
—
CAS0, 1
IACK1, 2
CS7
IACK7
AVEC or
(AVECO)/
IACK5
00000000
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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