Parallel I/O Ports
MC68360 USER’S MANUAL
7.14.4 Port A Registers
Port A has four memory-mapped, read-write, 16-bit control registers.
7.14.4.1 PORT A OPEN-DRAIN REGISTER (PAODR). The PAODR indicates a normal or
wired-OR configuration of the port pins. Six of the PAODR bits can be open-drain to corre-
spond to those pins that have serial channel output capability. The other bits are always
zero. PAODR is cleared at system reset.
For each ODx bit, the definition is as follows:
0 = The I/O pin is actively driven as an output.
1 = The I/O pin is an open-drain driver. As an output, the pin is actively driven low, but
in three-stated otherwise.
7.14.4.2 PORT A DATA REGISTER (PADAT). A read of PADAT returns the data at the
pin, independent of whether the pin is defined as an input or an output. This allows detection
of output conflicts at the pin by comparing the written data with the data on the pin. A write
to the PADIR is latched, and if that bit in the PADIR is configured as an output, the value
latched for that bit will be driven onto its respective pin. PADAT can be read or written at any
time. PADAT is not initialized and is undefined at reset.
7.14.4.3 PORT A DATA DIRECTION REGISTER (PADIR). PADIR is cleared at system
reset.
For each DRx bit, the definition is as follows:
0 = The corresponding pin is an input.
1 = The corresponding pin is an output.
7.14.4.4 PORT A PIN ASSIGNMENT REGISTER (PAPAR). PAPAR is cleared at system
reset.
15
14
13
12
11
10
9876543210
00000000
OD7
OD6
OD5
OD4
OD3
0
OD1
0
15
14
13
12
11
10
9876543210
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
15
14
13
12
11
10
9876543210
DR15
DR14
DR13
DR12
DR11
DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
15
14
13
12
11
10
9876543210
DD15
DD14
DD13
DD12
DD11
DD10
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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