![](http://datasheet.mmic.net.cn/30000/MC68EN360FE33_datasheet_2368935/MC68EN360FE33_725.png)
Applications
MC68360 USER’S MANUAL
9.1.2.2 REGULAR EPROM. Figure 9-2 shows the glueless interface to standard EPROM in
the system. In this case, an 8-bit boot EPROM is used. All accesses to the EPROM, even
word or long-word length, will be partitioned into multiple byte accesses to the EPROM.
The fact that the CONFIG2–CONFIG0 pins are pulled high causes these pins to default to
the 111 condition, selecting the CPU32+ core to be enabled, the CS0 pin to select a byte
port size, and the MBAR to be located in its normal address location. This is the most com-
monly used configuration for the CONFIGx pins. The pullups are used to allow for some of
the alternate functions of the CONFIGx pins to be used in later applications.
During initialization, CS0 should be programmed to respond to a 128-Kbyte area in this
design.
Figure 9-2. Glueless Interface to Standard EPROM
9.1.2.3 FLASH EPROM. Figure 9-3 shows the glueless interface to a flash EPROM device.
It is identical to the regular EPROM except that it allows for write operations as well. This
design assumes that the write operations are CE controlled, rather than WE controlled. Most
flash EPROM manufacturers now support this alternative timing method.
The fact that the CONFIGx pins are pulled high causes these pins to default to the 111 con-
dition, selecting the CPU32+ core to be enabled, the CS0 pin to select a byte port size, and
the MBAR to be located in its normal address location. This allows a byte-sized EPROM to
be used without any external glue logic.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
P
CE (ENABLE)
OE
BYTE
PORT SIZE
D31–D24
A16–A0
CS0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
+5V
SYSTEM BUS AND
QUICC-GENERATED SIGNALS
27C010
128K 8
EPROM
×
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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