Serial Communication Controllers (SCCs)
7-246
MC68360 USER’S MANUAL
Figure 7-69. QUICC Ethernet Parallel CAM Interface;
7.10.23.8 ETHERNET MEMORY MAP. When configured to operate in Ethernet mode, the
QUICC overlays the structure described in Table 7-5 onto the protocol-specific area of the
SCC parameter RAM described in Table 7-11.
QUICC
SCC
TxD
TENA (RTS)
TCLK (CLKx)
RxD
RENA (CD)
RCLK (CLKx)
CLSN (CTS)
RSTRT
RRJCT
PARALLEL I/O
TX
TENA
TCLK
RX
RENA
RCLK
CLSN
LOOP
PASSIVE
EEST
MC68160
TO MEDIA
CAM CONTROL
CAM
NOTE: The receive data is sent to the CAM as it is written to system memory. The SDACK2–SDACK1 signals are used to identify the
destination address and any other frame bytes desired. The RSTRT signal is not required in this configuration, although
it is still available.
SYSTEM BUS
SDACK2–SDACK1
DATA
46–1500 BYTES
DEST.
ADDR.
SOURCE
ADDR.
4 BYTES
2 BYTES
6 BYTES
SDACK2
SDACK1
RRJCT
FRAME CAN BE REJECTED IF ASSERTED
DURING FRAME RECEPTION. FURTHER
TRANSMISSIONS ON SYSTEM BUS CEASE,
AND BUFFER DESCRIPTORS ARE REUSED.
SDACK1 ASSERTED WHEN NEW FRAME
ARRIVES.
SDMA
BUS
WRITES
DEST.
ADDR.
2 BYTES
SIGNIFIES
LAST 32-BIT BUS WRITE
TO MEMORY ONLY IF TAG
BYTE IS APPENDED. TAG
BYTE COULD BE BYTE 0, 1, 2,
OR 3 OF THE 32-BIT WRITE.
ASSERTED FOR ONE
CYCLE OR TWO
16-BIT BUS WRITE
CYCLES, ETC.
PB15–PB8
OPTIONAL
FRAME TAG
BYTE
TAG
1 BYTE
(OPTIONAL)
ASSERTED ON EACH
WRITE CYCLE TO
MEMORY UP TO AND
INCLUDING THE
LAST SYSTEM BUS
WRITE OF THE
FRAME
NOTE: The diagram shows SDMA system bus writes, not data on the RXD pin. Other bus activity may occur between successive
32-bit writes. In such a case, the SDACK2–1 pins would not be asserted for other bus activity.
TYPE/
LENGTH
FRAME
CHECK
SEQUENCE
4 BYTES
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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