Bus Operation
MC68360 USER’S MANUAL
The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in
4.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences
are as follows:
1. FC3–FC0 are set to $7 (FC3/FC2/FC1/FC0 = 0111) for CPU address space.
2. A3, A2, and A1 are set to the interrupt request level, and the IACKx strobe correspond-
ing to the current interrupt level is asserted. (Either the function codes and address sig-
nals or the IACKx strobes can be monitored to determine that an interrupt
acknowledge cycle is in progress and the current interrupt level.)
3. The CPU32+ space type field (A19–A16) is set to $F (interrupt acknowledge).
4. Other address signals (A31–A20, A15–A4, and A0) are set to one.
The responding device places the vector number on the data bus during the interrupt
acknowledge cycle. Beyond this, the cycle is terminated normally with DSACKx.
for an interrupt acknowledge cycle terminated with DSACKx.
Figure 4-26. Interrupt Acknowledge Cycle Flowchart
START NEXT CYCLE
RELEASE
1) NEGATE DSACKx
QUICC
INTERRUPTING DEVICE
REQUEST INTERRUPT
GRANT INTERRUPT
PROVIDE VECTOR NUMBER
ACQUIRE VECTOR NUMBER
1) LATCH VECTOR NUMBER
2) NEGATE AS, DS, AND OE
1) SYNCHRONIZE IRQ7–IRQ1
2) COMPARE IRQ7–IRQ1 TO MASK LEVEL AND
WAIT FOR INSTRUCTION TO COMPLETE
3) ASSERT BCLRO
4) PLACE INTERRUPT LEVEL ON A1–A3;
TYPE FIELD (A19–A16) = $F
5) SET R/W TO READ
6) SET FC3–FC0 TO 0111
7) DRIVE SIZx PINS TO INDICATE A ONE-BYTE
TRANSFER
8) NEGATE BCLRO.
9) ASSERT AS, DS, AND OE
1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT
BYTE OF DATA PORT (DEPENDS ON
PORT SIZE)
2) ASSERT DSACKx (OR AVEC IF NO VECTOR
NUMBER)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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