![](http://datasheet.mmic.net.cn/30000/MC68EN360FE33_datasheet_2368935/MC68EN360FE33_141.png)
Bus Operation
MC68360 USER’S MANUAL
Once RESETH and RESETS negate, all control signals are driven to their inactive state, the
data bus is in read mode, and the address bus is driven. After this, the first bus cycle of the
reset exception processing begins.
Figure 4-47. Initial Reset Operation Timing
NOTE
The PLL samples the MODCLK pins while in the first 512 clocks
of RESET. The process starts with RESET being asserted, then
MODCLK pins are sampled and the PLL is initialized according
to the MODCLK pins. For the next 500-2000 EXTAL cycles the
PLL is synchronizing. 512 clocks after the PLL synchronizes, the
QUICC no longer drives RESET and does not sample the MOD-
CLK pins.
User should make suer the ramp up time of Vcc will never be
faster than 4mSec to ensure proper power on reset sequence.
When a RESET instruction is executed, the QUICC drives the RESETS signal for 512 clock
cycles. In this case, the QUICC resets the external devices of the system, and many of the
internal registers of the QUICC (see Section 3 QUICC Memory Map for a list of registers
affected by each type of reset).
The bus arbitration circuitry is only reset during a power-on reset. It may be used during all
other resets.
In QUICC slave mode (disable CPU32+) the reset operates the same as in the normal (mas-
ter) mode except that the RESET instruction does not exist.
CLKO1
VCO
LOCK
BUS
CYCLES
RESETH
VCC
1
23
4
BUS STATE
UNKNOWN
ADDRESS AND
CONTROL SIGNALS
THREE-STATED
512
CLKOUT
14 CLOCKS
≤
NOTES:
1. Internal start-up time.
2. SSP read here.
3. PC read here.
4. First instruction fetched here.
×
5. This figure is true when MODCK is 11 or 10.
When MODCK is 01 CLKO1 will be driven high at power up.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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