
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-27
NOTE
The guideline for selecting PSH and PSL is select is to maintain
approximately 50% duty cycle. So for prescaler values less then 16,
or PSH
≈ PSL. For prescaler values greater than 16 keep PSL as
large as possible.
Figure 5-8 shows that the prescaler is essentially a variable pulse width signal gener-
ator. A 5-bit down counter, clocked at the system clock rate, is used to create both the
high phase and the low phase of the QCLK signal. At the beginning of the high phase,
the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that
the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s com-
plement match with the 3-bit PSL value, which is the end of the low phase of the QCLK.
The PSA bit was maintained for software compatibility, but has no effect on QADC64.
The following equations define Qclk frequency:
High QCLK Time = (PSH + 1) ÷ FSYS
Low QCLK Time = (PSL + 1) ÷ FSYS
FQCLK = 1 ÷ (High QCLK Time + Low QCLK Time)
Where:
PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
F
SYS
= System clock frequency
F
QCLK = QCLK frequency
The following are equations for calculating the QCLK high and low phases in example
High QCLK Time = (11 + 1) ÷ 40 x106 = 300 ns
Low QCLK Time = (7 + 1) ÷ 40 x106 = 200 ns
FQCLK = 1/(300 + 200) = 2 Mhz
The following are equations for calculating the QCLK high and low phases in example
High QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
Low QCLK Time = (7 + 1) ÷ 32 x 106 = 250 ns
FQCLK = 1/(250 + 250) = 2 Mhz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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