
MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-34
When using 16 bits of resolution on the comparator (MODE[2:0] = 000), the output can
vary from a 0% duty cycle up to a duty cycle of 65535/65536. In this case it is not pos-
sible to have a 100% duty cycle. In cases where 16-bit resolution is not needed, it is
possible to have a duty cycle ranging from 0% to 100%. Setting bit 15 of the value
stored in register B to ‘1’ results in the output being ‘always set’. Clearing bit 15 (to ‘0’)
allows normal comparisons to occur and the normal output waveform is obtained.
Changes to and from the 100% duty cycle are done synchronously, as are all other
width changes.
In the OPWM mode, the WOR bit selects whether the output is totem pole driven or
open-drain.
13.5.3 DASM interrupts
When the FLAG bit is set, an interrupt request is generated on one of eight levels as
defined by the interrupt level bits (IL[2:0]) in the DASMSIC register. If the interrupt level
is set to zero, interrupts are disabled.
13.5.4 Freeze Action on the DASM
When the IMB FREEZE signal is recognized, the DASM capture and compare func-
tions are halted. As soon as the FREEZE signal is negated, DASM actions resume as
if nothing had happened. During freeze, the IN bit of the DASMSIC register is readable
Table 13-9 DASM PWM Example Output
Frequencies/Resolutions at fSYS = 16 MHz
NCPSM
NDASM
1
NOTES:
1. This table is valid only if the DASM is connected to a free-
running counter.
PWM output
frequency (Hz)
Resolution
(bits)
512
65536
0.48
16
2
65536
122.07
16
512
32768
0.95
15
2
32768
244.14
15
512
16384
1.91
14
2
16384
488.28
14
512
8192
3.81
13
2
8192
976.56
13
512
4096
7.63
12
2
4096
1953.13
12
512
2048
15.26
11
2
2048
3906.25
11
512
31.04
9
2
512
15625.00
9
512
128
244.14
7
2
128
62500.00
7
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Freescale Semiconductor, Inc.
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