
MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-31
4.4.9.2 Periodic Interrupt Timer Register
The PITR contains the count value for the periodic timer. This register can be read or written at any time.
4.5 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus
and external devices. Figure 4-9 shows a basic system with external memory and
peripherals.
The external bus has 24 address lines and 16 data lines. The EBI provides dynamic
sizing between 8-bit and 16-bit data accesses. It supports byte, word, and long-word
transfers. Port width is the maximum number of bits accepted or provided by the exter-
nal memory system during a bus transfer. Widths of eight and 16 bits are accessed
through the use of asynchronous cycles controlled by the size (SIZ1 and SIZ0) and
PICR — Periodic Interrupt Control Register
0xYF FA22
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
PIRQL[2:0]
PIV[7:0]
RESET:
0
1
Table 4-15 PICR Bit Descriptions
Bit(s)
Name
Description
15:11
—
Reserved
10:8
PIRQL
Periodic interrupt request level. This field determines the priority of periodic interrupt requests.
A value of 0b000 disables PIT interrupts.
7:0
PIV
Periodic interrupt vector. This field specifies the periodic interrupt vector number supplied by the
SCIM2 when the CPU32 acknowledges an interrupt request.
PITR — Periodic Interrupt Timer Register
0xYF FA24
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
PTP
PITM[7:0]
RESET:
0
MOD-
CLK
0
Table 4-16 PITR Bit Descriptions
Bit(s)
Name
Description
15:9
—
Reserved
8PTP
Periodic timer prescaler
0 = Periodic timer clock not prescaled.
1 = Periodic timer clock prescaled by a value of 512.
7:0
PITM
Periodic interrupt timing modulus. This field determines the periodic interrupt rate.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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