
MC68F375
CAN 2.0B CONTROLLER MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
7-19
frame awaiting transmission in any message buffer.
No CPU access to the TouCAN module.
The TouCAN is not in debug mode, low-power stop mode, or the bus off state.
While its clocks are stopped, if the TouCAN senses that any one of the aforementioned
conditions is no longer true, it restarts its clocks. The TouCAN then continues to mon-
itor these conditions and stops or restarts its clocks accordingly.
7.7 Interrupts
The TouCAN is capable of generating one interrupt level on the IMB3. This level is
programmed into the priority level bits in the interrupt configuration register (CANICR).
This value determines which interrupt signal is driven onto the bus when an interrupt
is requested.
When an interrupt is requested, the CPU32 initiates an IACK cycle. The TouCAN
decodes the IACK cycle and compares the CPU32 recognized level to the level that it
is currently requesting. If a match occurs, then arbitration begins. If the TouCAN wins
arbitration, it generates a uniquely encoded interrupt vector that indicates which event
is requesting service. This encoding scheme is as follows:
The higher-order bits of the interrupt vector come from the IVBA[2:0] field in CAN-
ICR.
The low-order five bits are an encoded value that indicate which of the 19 Tou-
CAN interrupt sources is requesting service.
Figure 7-5 shows a block diagram of the interrupt hardware.
Figure 7-5 TouCAN Interrupt Vector Generation
TOUCAN INTERRUPT GEN
INTERRUPT
REQUEST
LEVEL
MASKS
BUFFER
INTERRUPTS
BUS OFF
ERROR
WAKE UP
VECTOR
BASE
ADDRESS
(IVBA[2:0])
INTERRUPT
LEVEL
DECODER
INTERRUPT
PRIORITY
ENCODER
INTERRUPT
ENABLE
LOGIC
16
19
3
IRQ[7:1]
7
3
MODULE
INTERRUPT
VECTOR
5
19
3
(ILCAN[2:0]
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Freescale Semiconductor, Inc.
For More Information On This Product,
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