
MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-24
Figure 13-6 DASM Block Diagram
Channel A comprises one 16-bit data register and one 16-bit comparator. Channel B
also appears to the user to consist of one 16-bit data register and one 16-bit compar-
ator, however, internally, channel B has two data registers B1 and B2, and the
operating mode determines which register is accessed by the software:
In the input capture modes (IPWM, IPM and IC), registers A and B2 are used to
hold the captured values; in these modes, the B1 register is used as a temporary
latch for channel B.
In the output compare modes (OCA and OCAB), registers A and B2 are used to
define the output pulse; register B1 is not used in these modes.
In the output pulse width modulation mode (OPWM), registers A and B1 are used
as primary registers and hidden register B2 is used as a double buffer for channel
B.
Register contents are always transferred automatically at the correct time so that the
minimum pulse (measurement or generation) is just one time base bus count. The A
and B data registers are always read/write registers, accessible via the CTM’s sub-
module bus.
In the input capture modes, the edge detect circuitry triggers a capture whenever a ris-
ing or falling edge (as defined by the EDPOL bit) is applied to the input pin. The signal
on the input pin is Schmitt triggered and synchronized with the system clock (fSYS).
16-bit comparator A
IL2
IL0
IARB3
FLAG
2 time base buses
Interrupt
Bus
Control register bits
IN
FORCB
Submodule bus
control
select
Output
flip-flop
FORCA
I/O pin
Edge
detect
16-bit register A
BSL
MODE3 MODE2
IL1
Output
buffer
TBBB
TBBA
16-bit register B1
16-bit register B2
MODE1 MODE0
16-bit comparator B
WOR
EDPOL
Reg
ister
B
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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