
MC68F375
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
5-10
matically selected from the channel field of the conversion command word (CCW)
table, the same as internally multiplexed channels.
All of the automatic queue features are available for externally and internally multi-
plexed channels. The software selects externally multiplexed mode by setting the
MUX bit in QACR0.
Figure 5-3 shows the maximum configuration of four external multiplexers connected
to the QADC64. The external multiplexers select one of eight analog inputs and con-
nect it to one analog output, which becomes an input to the QADC64. The QADC64
provides three multiplexed address signals (MA[2:0]), to select one of eight inputs.
These outputs are connected to all four multiplexers. The analog output of each mul-
tiplexer is each connected to one of four separate QADC64 inputs — ANw, ANx, ANy,
and ANz.
Figure 5-3 Example of Full External Multiplexing
When the external multiplexed mode is selected, the QADC64 automatically creates
the MA[2:0] output signals from the channel number in each CCW. The QADC64 also
converts the proper input channel (ANw, ANx, ANy, and ANz) by interpreting the CCW
channel number. As a result, up to 32 externally multiplexed channels appear to the
AN52/MA0/PQA0
AN53/MA1/PQA1
AN54/MA2/PQA2
AN55/ETRIG1/PQA3
AN55/ETRIG2/PQA4
AN57/PQA5
AN58/PQA6
AN59/PQA7
AN0/ANW/PQB0
AN1/ANX/PQB1
AN2/ANY/PQB2
AN3/ANZ/PQB3
AN48/PQB4
AN49/PQB5
AN50/PQB6
AN51/PQB7
DIGITAL RESULTS
AND CONTROL
ANALOG
CONVERTER
ANALOG
MULTIPLEXER
VSSE
QADC64
VDDA
VSSA
VRL
VRH
MUX
AN0
AN2
AN4
AN6
AN8
AN10
AN12
AN14
MUX
AN1
AN3
AN5
AN7
AN9
AN11
AN13
AN15
MUX
AN16
AN18
AN20
AN22
AN24
AN26
AN28
AN30
MUX
AN17
AN19
AN21
AN23
AN25
AN27
AN29
AN31
ANALOG POWER
ANALOG REFERENCES
EXTERNAL TRIGGERS
PO
RT
B
PO
RT
A
V
DDH
ETRIG1
ETRIG2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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