
MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-5
16-bit counter. A software control register selects whether the clock input to the
counter is one of the taps from the prescaler or an input pin. The polarity of the external
input pin is also programmable. The free-running counter submodule operation is
comparable to the MC68HC11 counter.
A block diagram of the FCSM is shown in Figure 13-2. The main components of the
FCSM are a 16-bit loadable free-running up-counter, a clock selector, a time base bus
driver and an interrupt interface.
Figure 13-2 FCSM Block Diagram
NOTE
In order to be able to count, the FCSM requires the CPSM clock sig-
nals to be present. On coming out of reset, the FCSM will not count
internal or external events until the prescaler in the CPSM starts run-
ning (when the software sets the PRUN bit). This allows all counters
in the CTM submodules to be synchronized.
13.2.1 The FCSM Counter
The FCSM counter section comprises a 16-bit register and a 16-bit up-counter. Read-
ing the register transfers the contents of the counter to the data bus, while a write to
the register loads the counter with the new value. Overflow of the counter is defined to
be the transition from 0xFFFF to 0x0000. An overflow condition causes the COF flag
bit in the FCSMSIC register to be set.
NOTE
Reset presets the counter register to 0x0000. Writing 0x0000 to the
counter register while the counter’s value is 0xFFFF does not set the
16-bit up counter
IL2
IL1
IL0 IARB3
COF
Edge
Time base buses
Input pin
IL1
Interrupt
Clock
IN
CLK1 CLK0
CLK2
Overflow
Bus
Control register bits
DRVA DRVB
Control register bits
6 clocks (PCLKx) from prescaler
Submodule bus
control
select
detect
CTMC
TBBA
TBBB
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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