
MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-32
data size acknowledge (DSACK1 and DSACK0) pins. Multiple bus cycles may be
required for dynamically sized transfers.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic
is synchronized with EBI transfers. Refer to 4.9 Chip Selects for more information.
4.5.1 Bus Control Signals
The address bus provides addressing information to external devices. The data bus
transfers 8-bit and 16-bit data between the MCU and external devices. Strobe signals,
one for the address bus and another for the data bus, indicate the validity of an
address and provide timing information for data.
Control signals indicate the beginning of each bus cycle, the address space, the size
of the transfer, and the type of cycle. External devices can decode these signals and
respond to transfer data and terminate the bus cycle. The EBI can operate in an asyn-
chronous mode for any port width.
4.5.1.1 Address Bus
Bus signals ADDR[19:0] define the address of the byte (or the most significant byte)
to be transferred during a bus cycle. The MCU places the address on the bus at the
beginning of a bus cycle. The address is valid while AS is asserted.
4.5.1.2 Address Strobe
Address strobe (AS) is a timing signal that indicates the validity of an address on the
address bus as well as that of many control signals.
4.5.1.3 Data Bus
DATA[15:0] form a bidirectional, non-multiplexed parallel bus that transfers data to or
from the MCU. A read or write operation can transfer eight or 16 bits of data in one bus
cycle. For a write cycle, all 16 bits of the data bus are driven, regardless of the port
width or operand size.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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