
MC68F375
SINGLE-CHIP INTEGRATION MODULE 2 (SCIM2E)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
4-93
4.10.4.4 Port F Edge-Detect Flag Register
When the corresponding pin is configured for edge detection, a PORTFE bit is set if
an edge is detected. PORTFE bits remain set, regardless of the subsequent state of
the corresponding pin, until cleared. To clear a bit, first read PORTFE, then write the
bit to zero. When a pin is configured for general-purpose I/O or for use as an interrupt
request input, PORTFE bits do not change state. Bits [15:8] are reserved and will
always read zero.
4.10.4.5 Port F Edge-Detect Interrupt Vector
This register determines which vector in the exception vector table is used for inter-
rupts generated by the port F edge-detect logic. Program PFIVR[7:0] to the value
pointing to the appropriate interrupt vector. Bits [15:8] are reserved and will always
read zero.
4.10.4.6 Port F Edge-Detect Interrupt Level
This register determines the priority level of the port F edge-detect interrupt. The reset
value is 0x00, indicating that the interrupt is disabled. When several sources of inter-
rupts from the SCIM are arbitrating for the same level, the port F edge-detect interrupt
has the lowest arbitration priority. Bits [15:8] are reserved and will always read zero.
4.10.5 Port G
Port G is available in single-chip mode only. These pins are always configured for use
as general-purpose I/O in single-chip mode.
PORTFE — Port F Edge-Detect Flag Register
0xYF FA29
MSB
7
6
5
4
3
2
1
LSB
0
PEF7
PEF6
PEF5
PEF4
PEF3
PEF2
PEF1
PEF0
RESET:
0
PFIVR — Port F Edge-Detect Interrupt Vector Register
0xYF FA2B
MSB
7
6
5
4
3
2
1
LSB
0
PFIVR[7:0]
RESET:
0
PFLVR — Port F Edge-Detect Interrupt Level Register
0xYF FA2D
MSB
7
6
5
4
3
2
1
LSB
0
PFLV[2:0]
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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