
MC68F375
QUEUED SERIAL MULTI-CHANNEL MODULE
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
6-9
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial sub-
systems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock
source.)
The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins.
Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit
assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled,
TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete
input. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx
pin is assigned its SCI function.
The port QS data direction register (DDRQS) determines whether QSPI pins are
inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit
makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 6-10 summarizes the effect of DDRQS bits on QSPI pin function.
DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx
pins are always inputs, regardless of whether they are functioning as SCI pins or as
PORTQS pins.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins
defined as outputs. PORTQS reads return data present on the pins. To avoid driving
undefined data, write the first data to PORTQS before configuring DDRQS.
Table 6-7 QSMCM Pin Control Registers
Address
Register
0x30 5014
QSMCM Port Data Register (PORTQS)
descriptions.
0x30 5016
PORTQS Pin Assignment Register (PQSPAR)
0x30 5017
PORTQS Data Direction Register (DDRQS)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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