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参数资料
型号： MPC8272ADS
厂商： Freescale Semiconductor
文件页数： 106/158页
文件大小： 0K
描述： KIT DEVELOPMENT MPC8272
标准包装： 1
类型： MPU
适用于相关产品： MPC8272
所含物品： 板
Interconnect Signals
Table 8-4. P1—CPM Expansion Connector (continued)
Pin No.
C18
Signal Name
FETH1TXEN (PB29)
Attribute
I/O, T.S.
Description
Fast-Ethernet 1 Transmit Enable (H). The PowerQUICC II will
assert (High) this line, to indicate data valid on the FETHTXD(3:0)
lines.
When the Fast-Ethernet port is disabled, this line may be used for
any available function of PB29.
C19
FETH1COL (PB27)
I/O, T.S.
Fast-Ethernet Port 1 Collision Detected (H). When this signal is
asserted (High) by the DM9161, while the ethernet port is enabled,
it indicates a Collision state over the line. When the DM9161 is in
Full-Duplex mode, this line is inactive.
When the Ethernet port is disabled, this line is tristated and may be
used for any available function of the PB27.
C20
FETH1CRS (PB26)
I/O, T.S.
Fast-Ethernet 1 Carrier Sense (H). When this signal is asserted
(High), while the Ethernet port is enabled and the DM9161 is in
half-duplex mode, it indicates that either the transmit or receive
media are non-idle. When the DM9161 is in either full-duplex or
repeater operation, it indicates that the receive medium is non-idle.
When the Ethernet port is disabled, this line may be used for any
available function of PB26.
C21
C22
C23
C24
C25
C26
C27
C28
C29
FETH2RXD3 (PB18)
FETH2RXD2 (PB19)
FETH2RXD1 (PB20)
FETH2RXD0 (PB21)
FETH2TXD0 (PB22)
FETH2TXD1 (PB23)
FETH2TXD2 (PB24)
FETH2TXD3 (PB25)
ATMRCLK
I/O, T.S.
I/O, T.S.
O, T.S.
Fast Ethernet 2 Receive Data (3:0). This is the MII receive data
bus. The DM9161 drives these lines according to rising edge of
FETH2RXCK.
When the ethernet port is disabled, these lines are tristated and
may be used for any available respective parenthesized function.
Fast Ethernet 2 Transmit Data (3:0). This is the MII transmit data
bus. The PowerQUICC II drives these lines according to rising
edge of FETH2TXCK.
When the ethernet port is disabled, these lines may be used for
any available respective function.
ATM Receive Clock. A divide by 8 of the ATM line clock recovered
by the ATM receive logic. Provided to assist Circuit Emulation Tool.
Enabled only when pin A29 of this connector is either not
connected or driven low. Otherwise, Tri-stated.
C30
GND
O
Digital Ground. Connected to main GND plane of the ADS.
C31
C32
D1
D2
D3
D4
PC31
PC30
PC29
PC28
I/O, T.S.
PowerQUICC II’s Port C (31:22) Parallel I/O lines. May be used to
any of their available functions.
D5
D6
MPC8272ADS User Guide
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