参数资料
型号: MPC8272ADS
厂商: Freescale Semiconductor
文件页数: 117/158页
文件大小: 0K
描述: KIT DEVELOPMENT MPC8272
标准包装: 1
类型: MPU
适用于相关产品: MPC8272
所含物品:
Interconnect Signals
Table 8-8. P2 — System Expansion Connector (continued)
Pin No.
D4
D5
Signal Name
EXPWE0#
EXPWE1#
Attribute
O
Description
Expansion Write Enable (0:1) (L). These are buffered GPCM Write
Enable lines (0:1). They are meant to qualify writes to GPCM
controlled 8/16 data bus width memory devices. This to provide
eased access to various communication transceivers.
EXPWE0# controls EXPD(0:7) while EXPWE1# controls
EXPD(8:15). These lines may also function as UPM controlled
Byte Select Lines, which allow control over almost any type of
memory device.
D6
D7
D8
D9
D10
D11
D12
D13
D14
GND
EXPGL0#
EXPGL1#
EXPGL2#
EXPGL3#
EXPGL4#
EXPGL5#
GND
EXPALE
O
O
O
O
Digital Ground. Connected to main GND plane of the ADS.
Expansion General Purpose Lines (0:5) (L). These are buffered
GPL(0:5)# lines which assist UPM control over memory device if
necessary. These are output only signals and therefore, do not
support H/W controlled UPM waits.
Digital Ground. Connected to main GND plane of the ADS.
Expansion address latch enable (H). This is the buffered
PowerQUICC II‘s ALE, provided for expansion board’s use.
D15
EXPCTL0
O
Expansion control line 0. This line is a buffered version of
PowerQUICC II’s BCTL0 (Bus Control Line 0) which serves as
W/R#, provided for expansion board’s use.
Chapter 8. Support
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