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| 型号： | MPC8272ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 52/158页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT MPC8272 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8272 |
| 所含物品： | 板 |
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Reset and Reset Configuration
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Internal MPC8272 source.
A soft reset, when generated, causes the MPC8272 to reset its internal logic while keeping
its hard-reset configuration and memory controller setup and then jumping to the Reset
vector in the exception table. Since soft-reset does not reset the refresh logic for dynamic
RAMs, their contents is preserved.
SRESET when asserted, is extended internally by the MPC8272 for an additional 512 bus
clock cycles at the end of which, the MPC8272 waits for 16 bus clock cycles and then
re-checks the state of the SRESET line.
SRESET is an open-drain signal and must be driven with an open-drain gate by every
external source driving it. Otherwise, contention occurs over that line, which might cause
permanent damage to either the boards’ logic or to the MPC8272 itself.
5.1.4.1
COP/JTAG Port Soft Reset
To provide convenient soft-reset capability for a COP/JTAG controller, SRESET line
appears at the COP/JTAG port connector - P21. The COP/JTAG controller may directly
generate Soft-reset by asserting (low) this line.
5.1.4.2
Manual Soft Reset
To allow run-time Soft-reset, when the COP controller is disconnected from the
MPC8272ADS and to support resident debuggers, a Soft Reset push-button is provided.
When the Soft Reset push-button is depressed, the SRESET line is asserted to the
MPC8272, generating a Soft Reset sequence.
Since the SRESET line may be driven internally by the MPC8272, it must be driven by an
open-drain gate, to avoid contention over that line. If off-board H/W connected to the
MPC8272ADS is to drive SRESET line, then, it should do so with an open-drain gate, this,
to avoid contention over this line.
5.1.4.3
Internal Sources Soft Reset
The only internal Soft-reset source is the COP/JTAG soft-reset, which may be generated
using Public JTAG instructions to shift active-value (‘0’) to the SRESET pin via the
boundary scan chain. This is not useful for run time.
5.1.5
PCI Bus Reset
The PCI Module in the MPC8272 can generate a reset signal dedicated for MPC8272
devices which reside on the PCI bus. This is a reset to the PCI bus which is initiated by the
PCI bus Host - the MPC8272 on this board. This reset can also be initiated by a Soft PCI
Reset by setting a dedicated bit in a PCI control register (consult the MPC8272 User
Manual for details).
MPC8272ADS User Guide
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| MPC8309-KIT | KIT EVALUATION FOR MPC830X |
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| MPC8349E-MITX-GP | KIT REFERENCE PLATFORM MPC8349E |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8272CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8272CVRB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRE | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRI | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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