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| 型号： | MPC8272ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 66/158页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT MPC8272 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8272 |
| 所含物品： | 板 |
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Communication Ports
5.10 Communication Ports
The MPC8272ADS has several communication ports, to allow convenient evaluation of the
CPM features. Obviously, it is not possible to provide all types of communication interfaces
supported by the CPM, but it is made convenient to connect any communication interface
devices to the MPC8272 via the CPM Expansion connectors, residing on the edge of the
board.
All CPM pins are visible on MICTOR connectors. In order to avoid long routes and stubs,
bus muxing devices are used to direct the CPM signals to a communication element
on-board or to the expansion connector. A signal that is used on-board, will not be visible
in the expansion connector and vise-versa. The control is done by enabling/disabling the
communication elements on-board.
The communication ports’ interfaces provided on the MPC8272ADS are listed below:
1. 155 Mbps ATM UNI on FCC1 (switchable with Fast ethernet) with Optical
interface, using the UTOPIA Level 2 interface - support for 8 bit in multi or single
PHY.
2. Two 100/10-Base-T Ports on FCC1 (switchable with ATM) and FCC2 with T.P.
interface, MII or RMII controlled.
3. Dual RS232 ports residing on SCC1 & SCC4.
4. USB port, 1.1 USB standard compliant, with speed control (12 or 1.5 Mbps) and
mode control (Host or slave).
5.10.1 ATM Port
To support the MPC8272s’ ATM controller, a 155.52Mbps User Network Interface (UNI)
is provided on board, connected to FCC1 of the MPC8272 via UTOPIA I/F. Use is done
with PM5384 S/UNI-155-ULTRA by PMC-SIERA. Although these transceivers are
capable of supporting 51.84Mbps rate, support is given to 155.52Mbps only. The PHY
supports UTOPIA level 2 which means support for 8 bit UTOPIA bus in single or multi
PHY mode. The control over the mode of UTOPIA bus connection is done through BCSR3.
The control over the transceiver is done using the microprocessor interface of the
transceiver, controlled by the MPC8272 memory controllers’ GPCM.
The ATM transceiver may be enabled / disabled at any time by writing ’0’ /’1’ respectively
to the ATMEN bit in BCSRx. When ATMEN is negated, (’1’) the microprocessor control
port is also detached from the MPC8272 and its associated FCC may be used off-board via
the expansion connectors.
The ATM transceiver reset input is driven by HRESET signal of the MPC8272, so that the
UNI is reset whenever a hard-reset sequence occurs. The UNI may also be reset by either
MPC8272ADS User Guide
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相关代理商/技术参数 |
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| MPC8272CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8272CVRB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRE | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRI | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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