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参数资料
| 型号： | MPC8272ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 46/158页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT MPC8272 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8272 |
| 所含物品： | 板 |
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Reset and Reset Configuration
The configuration master is determined upon the rising edge of PORST, according to the
state of RSTCONF signal, driven low on this board, to set the MPC8272 as a configuration
master.
After power-on reset negates, the hard-reset sequence starts, during which many other
different options are configured. Among these options are additional clock configuration
bits PCI_MODCKH(0:3), the most significant bits of the MODCK field, which determine
additional options for the clock generator. Although these bits are sampled whenever the
hard-reset sequence is entered, they are influential only once, after power-on reset. If a hard
reset sequence is entered later, MODCKH(0:3), although sampled, are 'don’t care'.
The PCI_MODCK signal, which is sampled concurrently with the PCI_MODCK(0:3) pins,
determines the PCI bus clock frequency (see Section 5.2.2, “PCI Clock”). When set high,
it divides the PCI bus frequency by two. When reset low, the PCI bus frequency is as
determined by the MODCK(1:3) and PCI_MODCKH(0:3) signals.
5.1.3
Hard Reset
Hard reset may be generated on the MPC8272ADS by the following sources:
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?
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COP/JTAG port
Manual hard reset
MPC8272’s internal sources
Hard-reset, when generated, causes the MPC8272 to reset all its internal hardware except
for PLL logic, re-acquires the Hard-reset configuration from its current source, and jumps
to the Reset vector in the exception table. Since hard-reset resets also the refresh logic for
dynamic RAMs, their content is lost as well.
HRESET when asserted, is extended internally by the MPC8272 for additional 512 bus
clock cycles at the end of which the MPC8272 waits for 16 bus clock cycles and then
re-checks the state of the HRESET line.
HRESET is an open-drain signal and must be driven with an open-drain gate by whichever
external source is driving it. Otherwise, contention occurs over that line, which might cause
permanent damage to either board logic or to the MPC8272 itself.
5.1.3.1
COP/JTAG Port Hard Reset
To provide convenient hard-reset capability for a COP/JTAG controller, HRESET line
appears at the COP/JTAG port connector. The COP/JTAG controller may directly generate
hard-reset by asserting (low) this line.
MPC8272ADS User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8272CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8272CVRB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRE | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRI | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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