参数资料
型号: MPC8272ADS
厂商: Freescale Semiconductor
文件页数: 57/158页
文件大小: 0K
描述: KIT DEVELOPMENT MPC8272
标准包装: 1
类型: MPU
适用于相关产品: MPC8272
所含物品:
Clock Generator
5.2
Clock Generator
The two main clock circuits on board are the following:
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5.2.1
MPC8272 system clock
PCI clock
MPC8272 Clock
The MPC8272 requires a single clock source as the main clock source. All MPC8272 60x
bus timings are referenced to the main clock input - CLKIN1. The main clock input is in
1:1 ratio to the bus clock, with internal skew elimination (PLL). Use is done with 100MHz
3.3V clock oscillator, which is connected to a low inter-skew buffer (U10) to split the load
between all various clock consumers on both boards.
Special care is taken to isolate and terminate the clock route between the on-board PLL and
the MPC8272 to provide a 'clean' clock input for proper operation. The main clock scheme
is shown in Figure 5-3.
MPC8272
CLOCK GEN.
60x SDRAM
100 MHZ
Low
Skew
BCSR
Buffers
EXPANSION
MICTOR
Figure 5-3. Main Clock Generator Scheme
5.2.2
PCI Clock
The PCI bus clock is derived internally from the main clock input CLKIN1. The generated
PCI clock is output from a PCI-dedicated PLL named DLL. That clock output is feeding an
on-board low-skew and fast clock distributor that distributes the PCI clock to all on-board
PCI devices. One of the outputs is fed back to the PCI clock to the MPC8272 through
CLKIN2 input. This clock input is driven to the DLL, which synchronizes the DLL output
clock to the CLKIN2 input clock and maintains low skew between the DLL output and
CLKIN2 input. All PCI bus timings are referenced to the CLKIN2 input clock. Special care
was taken when the board layout was done to keep all copper traces from the clock
distributor outputs at the same lengths, including the output that is fed back to CLKIN2.
This design is in compliance with the PCI standard to achieve bus synchronization and low
skew. The PCI clock scheme is shown in Figure 5-4.
Chapter 5. Module Design
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