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参数资料
| 型号： | MPC8272ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 67/158页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT MPC8272 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8272 |
| 所含物品： | 板 |
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Communication Ports
asserting ATM_RST bit in BCSR1 (see Table 5-8) or by asserting (’1’) the RESET bit in
the Master Reset and Identify / Load Meters register via the UNI microprocessor interface.
The UNI transmit and receive clocks are fed with a 19.44 MHz +/- 20 ppm, clock generator,
5 V powered, while the receive and transmit fifos’ clocks of the UTOPIA interface are
provided by the MPC8272. The MPC8272 can provide the same clock for both UTOPIA
transmit and receive or separate clocks for each, hard-configured 1 .
The ATM SAR is connected to the physical medium by an optical interface. Use is done
with HP’s HFBR 5805 optical interface, which operates at 1300 nm with up to 2 Km
transmission range.
The ATM PHY is connected to IRQ5 and generates an interrupt when an appropriate event
occurs.
5.10.2 100/10 Base T Ports
Two fast Ethernet ports with T.P. (100-Base-TX) I/F is provided on the MPC8272ADS.
These ports also support 10 Mbps ethernet (10-Base-T) via the same transceiver - the
DM9161 by Davicom.
The DM9161 are connected to FCC1 and FCC2 of the MPC8272 via MII or RMII interface,
which is used for both - devices’ control and data path. The initial configuration of the
DM9161 on the MPC8272ADS is set by external resistors - 100Base-Tx Full Duplex in MII
mode. The selection between MII/RMII for FCC1 and FCC2 is done by jumpers JP5 and
JP10 respectively. The DM9161 must be set to MII or RMII while in power-down.
The DM9161 reset input is driven by either asserting the FETH_RST bit in BCSR1 (see
Table 5-8) or by asserting a specific bit in an internal register by using MII I/F.
To allow external use of FCC1 and FCC2, their pins appear at the CPM expansion
connectors and the ethernet transceiver may be Disabled / Enabled at any time via the MIIs’
MDIO port.
The DM9161 is able to interrupt the PowerQUICC II via IRQ5 line. This line is shared also
with the CPM expansion connectors. Therefore, any tool that is connected to IRQ5, should
drive these lines with an Open Drain buffer.
5.10.2.1 DM9161 Control
The DM9161 is controlled via the MII management 2 port which is a 2 wire interface: a
clock (MDC) and a bidirectional data line (MDIO). This is in fact a bus, i.e., up to 32
devices may reside over it, while the protocol defines a 5-bit slave address field, which is
compared against the slave address set to each device by hardware during device reset,
according to the levels on some pins. On the board, the slave address is hard-set to b00000
1 Using
resistors.
2 Also
known as MII MDIO port.
Chapter 5. Module Design
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| MPC8309-KIT | KIT EVALUATION FOR MPC830X |
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| MPC8349E-MITX-GP | KIT REFERENCE PLATFORM MPC8349E |
| MPC8349E-MITXE | BOARD REFERENCE FOR MPC8349 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8272CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8272CVRB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRE | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRI | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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