参数资料
型号: MPC8272ADS
厂商: Freescale Semiconductor
文件页数: 72/158页
文件大小: 0K
描述: KIT DEVELOPMENT MPC8272
标准包装: 1
类型: MPU
适用于相关产品: MPC8272
所含物品:
Board Control and Status Register - BCSR
Table 5-8. BCSR1 Description (continued)
BIT
4
MNEMONIC
FETHIEN1
Function
Fast Ethernet Port 1 Initial Enable . When asserted ( low ) the DM9161’s
PON
DEF
1
ATT.
R,W
MII port, residing on FCC1, is enabled after Power-Up or after FETH_RST
is negated. When negated ( high ), the DM9161’s MII port is isolated after
Power-Up or after FETH_RST is negated and all i/f signals are tri-stated.
After initial value has been set, this signal has no influence over the
DM9161 and MII isolation may be controlled via MDIO 0.10 bit.
5
FETH1_RST
Fast Ethernet port 1 Reset . When active ( low ) the DM9161 is reset. This
1
R,W
line is also driven by HRESET signal of the MPC8272. Since MDDIS pin of
the DM9161 is driven low with this application, the negation of this signal
causes all the H/W configuration bits to be sampled for initial values and
device control is moved to the MDIO channel, which is the control path of
the MII port.
6
RS232EN_1
RS232 port 1 Enable . When asserted ( low ) the RS232 transceiver for port
1
R,W
1, is enabled. When negated, the RS232 transceiver for port 1, is in standby
mode and SCC1 pins are available for off-board use via the expansion
connectors.
7
RS232EN_2
RS232 port 2 Enable . When asserted ( low ) the RS232 transceiver for port
1
R,W
2, is enabled. When negated, the RS232 transceiver for port 2, is in standby
mode and SCC4 pins are available for off-board use via the expansion
connectors.
8 - 31
Reserved
Un-implemented
0
R
5.11.3 BCSR2 Board Control—Status Register 2
BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a
read- only register which may be read at any time 1 . BCSR2s’ various fields are described
Table 5-9. BCSR2 Description
BIT
0-7
MNEMONIC
TSTAT(0:7)
Function
Tool Status (0:7) . This field is reserved for external tool status report. The
PON
DEF
-
ATT.
R
exact meaning of each bit within this field is tool unique and therefore will be
documented separately per each tool. These signals are available at the
System expansion connector.
8 - 11
TOOLREV(0:3)
TOOL Revision (0:3) . This field may contain the revision code of an
R
external tool connected to the PowerQUICC II. The various combinations of
this field will be described per each tool users’ manual. These signals are
available at the System expansion connector. The revision option for the
external tools are shown in Table 5-15
1 Provided
that BCSR is not disabled.
MPC8272ADS User Guide
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