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参数资料
| 型号： | MPC8272ADS |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 47/158页 |
| 文件大小： | 0K |
| 描述： | KIT DEVELOPMENT MPC8272 |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC8272 |
| 所含物品： | 板 |
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Reset and Reset Configuration
5.1.3.2
Manual Hard Reset
To allow runtime hard-reset, when the COP controller is disconnected from the
MPC8272ADS, and to support resident debuggers, manual hard is facilitated. Depressing
both soft reset (SW7) and ABORT (SW6) buttons assert s the HRESET pin of the
MPC8272, generating a hard reset sequence.
Because the HRESET line may be driven internally by the MPC8272, it must be driven to
the MPC8272 with an open-drain gate. If off-board hardware connected to the
MPC8272ADS is to drive HRESET line, it should do so with an open-drain gate, to avoid
contention over this line.
When hard reset is generated, the MPC8272 is reset in a destructive manner, that is, the hard
reset configuration is re-sampled and all registers (except for the PLL’s) are reset, including
memory controller registers. This reset causes loss of dynamic memory contents.
To save on board’s real-estate, this button is not a dedicated one, but is shared with the
soft-reset button and the ABORT button. When both are depressed, hard reset is generated.
5.1.3.3
Internal Sources Hard Reset
The MPC8272 has internal sources that generate hard reset. Among these sources are the
following:
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Loss of lock reset. When one of the PLLs (core, CPM), is out of lock, hard-reset is
generated.
Check-stop reset. When the core enters a check-stop state from some reason, a hard
reset may be generated, depending on the CSRE bit in the RMR.
Bus monitor reset. When the bus monitor is enabled and a bus cycle is not
terminated, hard-reset is generated.
S/W Watch Dog Reset. When the S/W watch-dog is enabled, and application
software fails to perform its reset routine, it generates hard reset.
COP/JTAG Reset (Internal). Hard reset may be forced by driving the HRESET line
using the external pin’s scan chain. Not useful for run time.
The MPC8272 asserts a reset line HARD or SOFT for a period 512 clock cycles after a reset
source is identified. A hard reset sequence is followed by a soft reset sequence.
5.1.3.4
Hard Reset Configuration
When hard reset is applied to the MPC8272 (externally as well as internally), it samples the
hard reset configuration word. This configuration may be taken from an internal default, in
case RSTCONF is negated during HRESET asserted or taken from the Flash
/E2PROM/BCSR (MS 8 bits of the data bus) (in general, from any device residing on CS0)
in case RSTCONF signal is asserted along with HRESET. The default configuration word
Chapter 5. Module Design
相关PDF资料 |
PDF描述 |
|---|---|
| MPC8308-RDB | BOARD REF DESIGN MPC8308 |
| MPC8309-KIT | KIT EVALUATION FOR MPC830X |
| MPC8315E-RDB | PROCESSOR BOARD PWRQUICCII PBGA |
| MPC8349E-MITX-GP | KIT REFERENCE PLATFORM MPC8349E |
| MPC8349E-MITXE | BOARD REFERENCE FOR MPC8349 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MPC8272CVR | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:MPC8272 PowerQUICC II Family Hardware Specifications |
| MPC8272CVRB | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRE | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRI | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
| MPC8272CVRM | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:PowerQUICC II⑩ Family Hardware Specifications |
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