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参数资料
| 型号： | MT46V4M32 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 15/66页 |
| 文件大小： | 1921K |
| 代理商： | MT46V4M32 |
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15
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
READs
READ bursts are initiated with a READ command,
as shown in Figure 6.
The starting column and bank addresses are pro-
vided with the READ command and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid nominally
at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 7 shows general
timing for each possible CAS latency setting. DQS is
driven by the DDR SDRAM along with output data.
The initial LOW state on DQS is known as the read
preamble; the LOW state coincident with the last data-
out element is known as the read postamble.
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go
High-Z. A detailed explanation of
t
DQSQ (valid data-
out skew),
t
QH (data-out window hold), the valid data
window are depicted in Figure 27. A detailed explana-
tion of
t
DQSCK (DQS transition skew to CK) and
t
AC
(data-out transition skew to CK) is depicted in Figure
28.
Data from any READ burst may be concatenated
with or truncated with data from a subsequent READ
command. In either case, a continuous flow of data can
be maintained. The first data element from the new
burst follows either the last element of a completed
burst or the last desired data element of a longer burst
which is being truncated. The new READ command
should be issued
x
cycles after the first READ com-
mand, where
x
equals the number of desired data ele-
ment pairs (pairs are required by the 2
n
-prefetch ar-
chitecture). This is shown in Figure 8. A READ com-
mand can be initiated on any clock cycle following a
previous READ command. Nonconsecutive read data
is shown for illustration in Figure 9. Full-speed random
read accesses within a page (or pages) can be performed
as shown in Figure 10.
Figure 6
READ Command
CS#
WE#
CAS#
RAS#
CKE
CA
A0-A7
A8
BA0,1
HIGH
EN AP
DIS AP
BA
A9, A10, A11
CK
CK#
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON T CARE
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PDF描述 |
|---|---|
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V4M32LG | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
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