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| 型号： | MT46V4M32 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 8/66页 |
| 文件大小： | 1921K |
| 代理商： | MT46V4M32 |
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8
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
Figure 1
Mode Register Definition
Burst Length
Read and write accesses to the DDR SDRAM are
burst oriented, with the burst length being programmable,
as shown in Figure 1. The burst length determines the
maximum number of column locations that can be ac-
cessed for a given READ or WRITE command. Burst
lengths of 2, 4, or 8 locations are available for both the
sequential and the interleaved burst types. Full page burst
is supported in sequential mode only.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached. The block is uniquely se-
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Normal Operation
Normal Operation/Reset DLL
All other states reserved
0
1
-
0
0
-
0
0
-
0
0
-
0
0
-
Valid
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
4
5
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency BT
0* 0*
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Operating Mode
A10
A11
BA1
BA0
10
11
12
13
* M13 and M12 (BA0 and BA1)
must be 0, 0 to select the
base mode register (vs. the
extended mode register).
M9
M10
M11
Order of Accesses Within a Burst
Burst
Length
Starting Column
Address
Type = Sequential Type = Interleaved
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
2
0-1
1-0
0-1
1-0
A1
0
0
1
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
A2 A1
0
0
0
0
1
1
1
1
n = A0 - A7,
A0 = 0
0
0
1
1
0
0
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
…Cn-1,
Cn…
Cn, Cn-1, Cn-2
Cn-3, Cn-4...
…Cn+1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Full
Page
(256)
Not supported
n = A0 - A7,
A0 = 1
Not supported
Table 1
Burst Definition
NOTE:
1. For a burst length of two, A1-A7 select the block
of two burst; A0 selects the starting column
within the block.
2. For a burst length of four, A2-A7 select the block
of four burst; A0-A1 select the starting column
within the block.
3. For a burst length of eight, A3-A7 select the
block of eight burst; A0-A2 select the starting
column within the block.
4. For a full-page burst, the full row is selected and
A0-A7 select the starting column. A0 also selects
the direction of the burst (incrementing if A0 = 0,
decrementing if A0 = 1).
5. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
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