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42
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
CK
CK#
2.80V
2
3
5
5
Maximum Clock Level
Minimum Clock Level
4
- 0.30V
1.25V
1.45V
1.05V
V
ID
(AC)
V
ID
(DC)
X
X
1
V
MP
(DC)
V
IX
(AC)
NOTE:
1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of V
DD
Q.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least V
ID
(DC) min when static and is centered around V
MP
(DC)
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than V
DD
Q + 0.3V or more negative than Vss - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
X
X
CLOCK INPUT OPERATING CONDITIONS
(Notes: 1–5, 15, 16, 30; notes appear on pages 46–49) (0°C
≤
T
A
≤
+ 70°C; V
DD
= +2.5V ±0.125V, V
DD
Q = +2.5V ±0.125V)
PARAMETER/CONDITION
Clock Input Mid-Point Voltage; CK and CK#
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
V
MP
(
DC
)
V
IN
(
DC
)
V
ID
(
DC
)
V
ID
(
AC
)
V
IX
(
AC
)
MIN
1.15
-0.3
0.36
0.7
MAX
1.35
UNITS
V
V
V
V
V
NOTES
6, 9
6
6, 8
8
9
V
DD
Q + 0.3
V
DD
Q + 0.6
V
DD
Q + 0.6
0.5 x V
DD
Q + 0.2
0.5 x V
DD
Q - 0.2
Figure 27
SSTL_2 Clock Input