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参数资料
| 型号： | MT46V4M32 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 47/66页 |
| 文件大小： | 1921K |
| 代理商： | MT46V4M32 |
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47
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
24. The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maximum
amount for any given device.
25. The valid data window is derived by achieving
other specifications -
t
HP (
t
CK/2),
t
DQSQ,
and
t
QH [
t
HP - 0.4ns (-3),
t
HP - 0.4ns (-4) or
t
HP -
0.5ns (-4)]. The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: DQS with DQ0-
DQ31
27. This limit is actually a nominal value and does
not result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
28. The DC values define where the input slew rate
requirements are imposed, and the input signal
must not violate these levels in order to maintain
NOTES (continued)
a valid level. The inputs require the AC value to
be achieved during signal transition edge and
the driver should achieve the same slew rate
through the AC values.
29. The Input capacitance per pin group will not
differ by more than this maximum amount for
any given device..
30. CK and CK# input slew rate must be
≥
1V/ns.
31. DQ and DM input slew rates must not deviate
from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing is no longer
referenced to the mid-point but to the V
IL
(
AC
)
maximum and V
IH
(
AC
) minimum points.
32. Vdd must not vary more than 4% if CKE is not
active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
34.
t
HP (MIN) is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and CK/
inputs, collectively during bank active.
DERATING DATA VALID WINDOW
(
t
QH -
t
DQSQ)
t
0.850
0.834
0.817
0.801
0.784
0.768
0.751
0.735
0.718
0.702
0.685
1.150
1.130
1.110
1.090
1.070
1.050
1.030
1.010
0.990
0.970
0.950
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
n
-33 @ tCK = 3.3ns
-4 @ tCK = 4ns
-5 @ tCK = 5ns
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