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49
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
NOTES (continued)
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within
the inner bounding lines of the V-I curve of
FiguresC and C.
e)The full variation in the ratio of the maximum
to minimum pull-up and pull-down current
will not exceed 1.7, for device drain-to-source
voltages from 0 to V
DD
Q/2.
f) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±30%, for device drain-to-source voltages from
0 to V
DD
Q/2.
38. The voltage levels used are derived from the
refernced test load. In practice, the voltage levels
obtained from a properly terminated bus will
provide significantly different voltage values.
39. V
IH
overshoot: VIH (MAX) = V
DD
Q+1.5V for a pulse
width
≤
3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
IL
undershoot:
V
IL
(MIN) = -1.5V for a pulse width
≤
3ns and the
pulse width can not be greater than 1/3 of the
cycle rate.
40. All speed grades support CL 2, 3, 4, and 5 but only
the speed grades listed in the AC timing tables are
tested.
41. The DLL must be reset when changing the
frequency.
42. V
DD
and V
DD
Q must track each other.
Figure D
Pull-Up
Figure C
Pull-Down
Vout (V)
I
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
Nominal Low
Nominal High
MIN
MAX
Vout (V)
I
-120
-100
-80
-60
-40
-20
0
0.0
0.5
1.0
1.5
2.0
2.5
Nominal Low
Nominal High
MIN
MAX