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参数资料
| 型号： | MT46V4M32 |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 双倍数据速率的DDR SDRAM内存 |
| 文件页数： | 2/66页 |
| 文件大小： | 1921K |
| 代理商： | MT46V4M32 |
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128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
GENERAL DESCRIPTION
The 128Mb (x32) DDR SDRAM is a high-speed
CMOS, dynamic random-access memory containing
134,217,728- bits. It is internally configured as a quad-
bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2
n
-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 128Mb DDR SDRAM
effectively consists of a single 2
n
-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding
n
-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
The 128Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, 8, or full page locations.
An auto precharge function may be enabled to provide
a self-timed row precharge that is initiated at the end of
the burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class I compatible.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise.
相关PDF资料 |
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|---|---|
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4组,双数据速率同步动态RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4组,双数据速率同步动态RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT46V4M32LG | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全称:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
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