参数资料
型号: MT48H8M16LFB4-75:K TR
厂商: Micron Technology Inc
文件页数: 14/63页
文件大小: 0K
描述: IC SDRAM 128MBIT 133MHZ 54VFBGA
标准包装: 1
格式 - 存储器: RAM
存储器类型: 移动 SDRAM
存储容量: 128M(8Mx16)
速度: 133MHz
接口: 并联
电源电压: 1.7 V ~ 1.95 V
工作温度: 0°C ~ 70°C
封装/外壳: 54-VFBGA
供应商设备封装: 54-VFBGA(8x8)
包装: 标准包装
其它名称: 557-1531-6
128Mb: x16 Mobile SDRAM
Commands
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operation” on page 17; these tables provide current state/next state information.
Table 5:
Truth Table 1 – Commands and DQM Operation
Note 1; notes appear below table
Name (Function)
CS#
RAS# CAS#
WE#
DQM
ADDR
DQs
Notes
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
H
L
X
H
X
H
X
H
X
X
X
X
X
X
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
L
L
L
L
L
H
H
H
H
L
L
H
H
H
L
L
X
L/H
L/H
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
Valid
X
2
3
3
4, 5
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
L
L
L
L
H
L
L
H
X
X
Bank, A10
X
X
X
6
7, 8
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
L
L
L
L
X
Op-Code
X
9
REGISTER
Write enable/output enable
Write inhibit/output High-Z
X
X
X
X
X
X
X
X
L
H
X
X
Active
High-Z
10
10
Notes:
1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persis-
tent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
4. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is
LOW.
5. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
could coincide with data on the bus. However, the DQs column reads a “Don’t Care” state
to illustrate that the BURST TERMINATE command can occur when there is no data present.
6. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
charged and BA0, BA1 are “Don’t Care.”
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
9. A0-A11 define op-code written to mode register.
10. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay). LDQM controls DQ0–7, UDQM controls DQ8–15.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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