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参数资料
| 型号： | MT48H8M16LFB4-75:K TR |
| 厂商： | Micron Technology Inc |
| 文件页数： | 9/63页 |
| 文件大小： | 0K |
| 描述： | IC SDRAM 128MBIT 133MHZ 54VFBGA |
| 标准包装： | 1 |
| 格式 - 存储器： | RAM |
| 存储器类型： | 移动 SDRAM |
| 存储容量： | 128M（8Mx16） |
| 速度： | 133MHz |
| 接口： | 并联 |
| 电源电压： | 1.7 V ~ 1.95 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 54-VFBGA |
| 供应商设备封装： | 54-VFBGA（8x8） |
| 包装： | 标准包装 |
| 其它名称： | 557-1531-6 |
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MRD before initiating the subsequent operation. Violating either of these requirements
128Mb: x16 Mobile SDRAM
Mode Register Definition
The mode register must be loaded when all banks are idle, and the controller must wait
t
will result in unspecified operation.
Figure 4:
Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13
0
12 11 10 9 8 7 6 5 4
0 Reserved 1 WB OP Mode CAS Latency
3 2 1 0
BT Burst Length
Mode
Register (Mx)
M13 M12 Mode Register Definintion
Burst Length
0
0
Base mode register
M2 M1 M0
M3 = 0
M3 = 1
0
1
1
1
0
1
Reserved
Extended mode register
Reserved
0
0
0
0
0
1
0
1
0
1
2
4
1
2
4
0
1
1
8
8
M9
0
1
Write Burst Mode
Programmed burst length
Single location access
1
1
1
1
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
M8 M7
M6–M0
Operating Mode
0
0
Defined
Normal operation
–
–
–
All other states reserved
CAS Latency
M6 M5 M4
Reserved
0 0 0
Reserved
0
0
1
2
0
1
0
3
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
M3
0
1
Burst Type
Sequential
Interleaved
Notes:
1. Must be programmed “0,0” to ensure compatibility with future devices.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 4. BL determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. BLs of 1, 2, 4, or 8 locations are avail-
able for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is selected.
All accesses for that burst take place within this block, meaning that the burst will wrap
within the block if a boundary is reached. The block is uniquely selected by A1–A8 when
BL = 2; by A2–A8 when BL = 4; and by A3–A8 when BL = 8. The remaining (least signifi-
cant) address bit(s) is (are) used to select the starting location within the block.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48H8M16LFB4-8 | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT | 制造商:Micron Technology Inc 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA |
| MT48H8M16LFB4-8 IT TR | 功能描述:IC SDRAM 128MBIT 125MHZ 54VFBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:96 系列:- 格式 - 存储器:闪存 存储器类型:FLASH 存储容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并联 电源电压:2.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 |
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